用户登录和接口鉴权

2025-09-07 21:13:15 +08:00
parent c4522b974b
commit 565cf3fa6a
380 changed files with 18330 additions and 16854 deletions
--- a/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
+++ b/vendor/github.com/klauspost/cpuid/v2/.goreleaser.yml
@@ -1,4 +1,5 @@
-version: 2
+# This is an example goreleaser.yaml file with some sane defaults.
+# Make sure to check the documentation at http://goreleaser.com

 builds:
  -
@@ -26,7 +27,16 @@ builds:
 archives:
  -
    id: cpuid
-    name_template: "cpuid-{{ .Os }}_{{ .Arch }}{{ if .Arm }}v{{ .Arm }}{{ end }}"
+    name_template: "cpuid-{{ .Os }}_{{ .Arch }}_{{ .Version }}"
+    replacements:
+      aix: AIX
+      darwin: OSX
+      linux: Linux
+      windows: Windows
+      386: i386
+      amd64: x86_64
+      freebsd: FreeBSD
+      netbsd: NetBSD
    format_overrides:
      - goos: windows
        format: zip
@@ -34,6 +44,8 @@ archives:
      - LICENSE
 checksum:
  name_template: 'checksums.txt'
+snapshot:
+  name_template: "{{ .Tag }}-next"
 changelog:
  sort: asc
  filters:
@@ -46,7 +58,7 @@ changelog:

 nfpms:
  -
-    file_name_template: "cpuid_package_{{ .Os }}_{{ .Arch }}{{ if .Arm }}v{{ .Arm }}{{ end }}"
+    file_name_template: "cpuid_package_{{ .Version }}_{{ .Os }}_{{ .Arch }}"
    vendor: Klaus Post
    homepage: https://github.com/klauspost/cpuid
    maintainer: Klaus Post <klauspost@gmail.com>
@@ -55,3 +67,8 @@ nfpms:
    formats:
      - deb
      - rpm
+    replacements:
+      darwin: Darwin
+      linux: Linux
+      freebsd: FreeBSD
+      amd64: x86_64
--- a/vendor/github.com/klauspost/cpuid/v2/README.md
+++ b/vendor/github.com/klauspost/cpuid/v2/README.md
@@ -281,11 +281,7 @@ Exit Code 1
 | AMXBF16            | Tile computational operations on BFLOAT16 numbers                                                                                                                                  |
 | AMXINT8            | Tile computational operations on 8-bit integers                                                                                                                                    |
 | AMXFP16            | Tile computational operations on FP16 numbers                                                                                                                                      |
-| AMXFP8             | Tile computational operations on FP8 numbers                                                                                                                                       |
-| AMXCOMPLEX         | Tile computational operations on complex numbers                                                                                                                                   |
 | AMXTILE            | Tile architecture                                                                                                                                                                  |
-| AMXTF32            | Matrix Multiplication of TF32 Tiles into Packed Single Precision Tile                                                                                                              |
-| AMXTRANSPOSE       | Tile multiply where the first operand is transposed                                                                                                                                |
 | APX_F              | Intel APX                                                                                                                                                                          |
 | AVX                | AVX functions                                                                                                                                                                      |
 | AVX10              | If set the Intel AVX10 Converged Vector ISA is supported                                                                                                                           |
@@ -314,7 +310,6 @@ Exit Code 1
 | AVXSLOW            | Indicates the CPU performs 2 128 bit operations instead of one                                                                                                                     |
 | AVXVNNI            | AVX (VEX encoded) VNNI neural network instructions                                                                                                                                 |
 | AVXVNNIINT8        | AVX-VNNI-INT8 instructions                                                                                                                                                         |
-| AVXVNNIINT16       | AVX-VNNI-INT16 instructions                                                                                                                                                        |
 | BHI_CTRL           | Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598                                                                    |
 | BMI1               | Bit Manipulation Instruction Set 1                                                                                                                                                 |
 | BMI2               | Bit Manipulation Instruction Set 2                                                                                                                                                 |
@@ -418,12 +413,9 @@ Exit Code 1
 | SEV_SNP            | AMD SEV Secure Nested Paging supported                                                                                                                                             |
 | SGX                | Software Guard Extensions                                                                                                                                                          |
 | SGXLC              | Software Guard Extensions Launch Control                                                                                                                                           |
-| SGXPQC             | Software Guard Extensions 256-bit Encryption                                                                                                                                       |
 | SHA                | Intel SHA Extensions                                                                                                                                                               |
 | SME                | AMD Secure Memory Encryption supported                                                                                                                                             |
 | SME_COHERENT       | AMD Hardware cache coherency across encryption domains enforced                                                                                                                    |
-| SM3_X86            | SM3 instructions                                                                                                                                                                   |
-| SM4_X86            | SM4 instructions                                                                                                                                                                   |
 | SPEC_CTRL_SSBD     | Speculative Store Bypass Disable                                                                                                                                                   |
 | SRBDS_CTRL         | SRBDS mitigation MSR available                                                                                                                                                     |
 | SSE                | SSE functions                                                                                                                                                                      |
@@ -451,9 +443,6 @@ Exit Code 1
 | TLB_FLUSH_NESTED   | AMD: Flushing includes all the nested translations for guest translations                                                                                                          |
 | TME                | Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.                         |
 | TOPEXT             | TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.                                                         |
-| TSA_L1_NO          | AMD only: Not vulnerable to TSA-L1                                                                                                                                                 |
-| TSA_SQ_NO          | AMD only: Not vulnerable to TSA-SQ                                                                                                                                                 |
-| TSA_VERW_CLEAR     | AMD: If set, the memory form of the VERW instruction may be used to help mitigate TSA                                                                                              |
 | TSCRATEMSR         | MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104                                                                                                       |
 | TSXLDTRK           | Intel TSX Suspend Load Address Tracking                                                                                                                                            |
 | VAES               | Vector AES. AVX(512) versions requires additional checks.                                                                                                                          |
@@ -489,16 +478,12 @@ Exit Code 1
 | DCPOP        | Data cache clean to Point of Persistence (DC CVAP)               |
 | EVTSTRM      | Generic timer                                                    |
 | FCMA         | Floatin point complex number addition and multiplication         |
-| FHM          | FMLAL and FMLSL instructions                                     |
 | FP           | Single-precision and double-precision floating point             |
 | FPHP         | Half-precision floating point                                    |
 | GPA          | Generic Pointer Authentication                                   |
 | JSCVT        | Javascript-style double->int convert (FJCVTZS)                   |
 | LRCPC        | Weaker release consistency (LDAPR, etc)                          |
 | PMULL        | Polynomial Multiply instructions (PMULL/PMULL2)                  |
-| RNDR         | Random Number instructions                                       |
-| TLB          | Outer Shareable and TLB range maintenance instructions           |
-| TS           | Flag manipulation instructions                                   |
 | SHA1         | SHA-1 instructions (SHA1C, etc)                                  |
 | SHA2         | SHA-2 instructions (SHA256H, etc)                                |
 | SHA3         | SHA-3 instructions (EOR3, RAXI, XAR, BCAX)                       |
--- a/vendor/github.com/klauspost/cpuid/v2/cpuid.go
+++ b/vendor/github.com/klauspost/cpuid/v2/cpuid.go
@@ -55,12 +55,6 @@ const (
 	Qualcomm
 	Marvell

-	QEMU
-	QNX
-	ACRN
-	SRE
-	Apple
-
 	lastVendor
 )

@@ -81,11 +75,7 @@ const (
 	AMXBF16                              // Tile computational operations on BFLOAT16 numbers
 	AMXFP16                              // Tile computational operations on FP16 numbers
 	AMXINT8                              // Tile computational operations on 8-bit integers
-	AMXFP8                               // Tile computational operations on FP8 numbers
 	AMXTILE                              // Tile architecture
-	AMXTF32                              // Tile architecture
-	AMXCOMPLEX                           // Matrix Multiplication of TF32 Tiles into Packed Single Precision Tile
-	AMXTRANSPOSE                         // Tile multiply where the first operand is transposed
 	APX_F                                // Intel APX
 	AVX                                  // AVX functions
 	AVX10                                // If set the Intel AVX10 Converged Vector ISA is supported
@@ -114,7 +104,6 @@ const (
 	AVXSLOW                              // Indicates the CPU performs 2 128 bit operations instead of one
 	AVXVNNI                              // AVX (VEX encoded) VNNI neural network instructions
 	AVXVNNIINT8                          // AVX-VNNI-INT8 instructions
-	AVXVNNIINT16                         // AVX-VNNI-INT16 instructions
 	BHI_CTRL                             // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598
 	BMI1                                 // Bit Manipulation Instruction Set 1
 	BMI2                                 // Bit Manipulation Instruction Set 2
@@ -220,12 +209,9 @@ const (
 	SEV_SNP                              // AMD SEV Secure Nested Paging supported
 	SGX                                  // Software Guard Extensions
 	SGXLC                                // Software Guard Extensions Launch Control
-	SGXPQC                               // Software Guard Extensions 256-bit Encryption
 	SHA                                  // Intel SHA Extensions
 	SME                                  // AMD Secure Memory Encryption supported
 	SME_COHERENT                         // AMD Hardware cache coherency across encryption domains enforced
-	SM3_X86                              // SM3 instructions
-	SM4_X86                              // SM4 instructions
 	SPEC_CTRL_SSBD                       // Speculative Store Bypass Disable
 	SRBDS_CTRL                           // SRBDS mitigation MSR available
 	SRSO_MSR_FIX                         // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO.
@@ -256,9 +242,6 @@ const (
 	TLB_FLUSH_NESTED                     // AMD: Flushing includes all the nested translations for guest translations
 	TME                                  // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
 	TOPEXT                               // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
-	TSA_L1_NO                            // AMD only: Not vulnerable to TSA-L1
-	TSA_SQ_NO                            // AM onlyD: Not vulnerable to TSA-SQ
-	TSA_VERW_CLEAR                       // If set, the memory form of the VERW instruction may be used to help mitigate TSA
 	TSCRATEMSR                           // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
 	TSXLDTRK                             // Intel TSX Suspend Load Address Tracking
 	VAES                                 // Vector AES. AVX(512) versions requires additional checks.
@@ -290,17 +273,13 @@ const (
 	CRC32    // CRC32/CRC32C instructions
 	DCPOP    // Data cache clean to Point of Persistence (DC CVAP)
 	EVTSTRM  // Generic timer
-	FCMA     // Floating point complex number addition and multiplication
-	FHM      // FMLAL and FMLSL instructions
+	FCMA     // Floatin point complex number addition and multiplication
 	FP       // Single-precision and double-precision floating point
 	FPHP     // Half-precision floating point
 	GPA      // Generic Pointer Authentication
 	JSCVT    // Javascript-style double->int convert (FJCVTZS)
 	LRCPC    // Weaker release consistency (LDAPR, etc)
 	PMULL    // Polynomial Multiply instructions (PMULL/PMULL2)
-	RNDR     // Random Number instructions
-	TLB      // Outer Shareable and TLB range maintenance instructions
-	TS       // Flag manipulation instructions
 	SHA1     // SHA-1 instructions (SHA1C, etc)
 	SHA2     // SHA-2 instructions (SHA256H, etc)
 	SHA3     // SHA-3 instructions (EOR3, RAXI, XAR, BCAX)
@@ -308,13 +287,6 @@ const (
 	SM3      // SM3 instructions
 	SM4      // SM4 instructions
 	SVE      // Scalable Vector Extension
-
-	// PMU
-	PMU_FIXEDCOUNTER_CYCLES
-	PMU_FIXEDCOUNTER_REFCYCLES
-	PMU_FIXEDCOUNTER_INSTRUCTIONS
-	PMU_FIXEDCOUNTER_TOPDOWN_SLOTS
-
 	// Keep it last. It automatically defines the size of []flagSet
 	lastID

@@ -323,22 +295,20 @@ const (

 // CPUInfo contains information about the detected system CPU.
 type CPUInfo struct {
-	BrandName              string  // Brand name reported by the CPU
-	VendorID               Vendor  // Comparable CPU vendor ID
-	VendorString           string  // Raw vendor string.
-	HypervisorVendorID     Vendor  // Hypervisor vendor
-	HypervisorVendorString string  // Raw hypervisor vendor string
-	featureSet             flagSet // Features of the CPU
-	PhysicalCores          int     // Number of physical processor cores in your CPU. Will be 0 if undetectable.
-	ThreadsPerCore         int     // Number of threads per physical core. Will be 1 if undetectable.
-	LogicalCores           int     // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
-	Family                 int     // CPU family number
-	Model                  int     // CPU model number
-	Stepping               int     // CPU stepping info
-	CacheLine              int     // Cache line size in bytes. Will be 0 if undetectable.
-	Hz                     int64   // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed.
-	BoostFreq              int64   // Max clock speed, if known, 0 otherwise
-	Cache                  struct {
+	BrandName      string  // Brand name reported by the CPU
+	VendorID       Vendor  // Comparable CPU vendor ID
+	VendorString   string  // Raw vendor string.
+	featureSet     flagSet // Features of the CPU
+	PhysicalCores  int     // Number of physical processor cores in your CPU. Will be 0 if undetectable.
+	ThreadsPerCore int     // Number of threads per physical core. Will be 1 if undetectable.
+	LogicalCores   int     // Number of physical cores times threads that can run on each core through the use of hyperthreading. Will be 0 if undetectable.
+	Family         int     // CPU family number
+	Model          int     // CPU model number
+	Stepping       int     // CPU stepping info
+	CacheLine      int     // Cache line size in bytes. Will be 0 if undetectable.
+	Hz             int64   // Clock speed, if known, 0 otherwise. Will attempt to contain base clock speed.
+	BoostFreq      int64   // Max clock speed, if known, 0 otherwise
+	Cache          struct {
 		L1I int // L1 Instruction Cache (per core or shared). Will be -1 if undetected
 		L1D int // L1 Data Cache (per core or shared). Will be -1 if undetected
 		L2  int // L2 Cache (per core or shared). Will be -1 if undetected
@@ -347,34 +317,8 @@ type CPUInfo struct {
 	SGX              SGXSupport
 	AMDMemEncryption AMDMemEncryptionSupport
 	AVX10Level       uint8
-	PMU              PerformanceMonitoringInfo //  holds information about the PMU
-
-	maxFunc   uint32
-	maxExFunc uint32
-}
-
-// PerformanceMonitoringInfo holds information about CPU performance monitoring capabilities.
-// This is primarily populated from CPUID leaf 0xAh on x86
-type PerformanceMonitoringInfo struct {
-	// VersionID (x86 only): Version ID of architectural performance monitoring.
-	// A value of 0 means architectural performance monitoring is not supported or information is unavailable.
-	VersionID uint8
-	// NumGPPMC: Number of General-Purpose Performance Monitoring Counters per logical processor.
-	// On ARM, this is derived from PMCR_EL0.N (number of event counters).
-	NumGPCounters uint8
-	// GPPMCWidth: Bit width of General-Purpose Performance Monitoring Counters.
-	// On ARM, typically 64 for PMU event counters.
-	GPPMCWidth uint8
-	// NumFixedPMC: Number of Fixed-Function Performance Counters.
-	// Valid on x86 if VersionID > 1. On ARM, this typically includes at least the cycle counter (PMCCNTR_EL0).
-	NumFixedPMC uint8
-	// FixedPMCWidth: Bit width of Fixed-Function Performance Counters.
-	// Valid on x86 if VersionID > 1. On ARM, the cycle counter (PMCCNTR_EL0) is 64-bit.
-	FixedPMCWidth uint8
-	// Raw register output from CPUID leaf 0xAh.
-	RawEBX uint32
-	RawEAX uint32
-	RawEDX uint32
+	maxFunc          uint32
+	maxExFunc        uint32
 }

 var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
@@ -558,7 +502,7 @@ func (c CPUInfo) FeatureSet() []string {
 // Uses the RDTSCP instruction. The value 0 is returned
 // if the CPU does not support the instruction.
 func (c CPUInfo) RTCounter() uint64 {
-	if !c.Has(RDTSCP) {
+	if !c.Supports(RDTSCP) {
 		return 0
 	}
 	a, _, _, d := rdtscpAsm()
@@ -570,22 +514,13 @@ func (c CPUInfo) RTCounter() uint64 {
 // about the current cpu/core the code is running on.
 // If the RDTSCP instruction isn't supported on the CPU, the value 0 is returned.
 func (c CPUInfo) Ia32TscAux() uint32 {
-	if !c.Has(RDTSCP) {
+	if !c.Supports(RDTSCP) {
 		return 0
 	}
 	_, _, ecx, _ := rdtscpAsm()
 	return ecx
 }

-// SveLengths returns arm SVE vector and predicate lengths in bits.
-// Will return 0, 0 if SVE is not enabled or otherwise unable to detect.
-func (c CPUInfo) SveLengths() (vl, pl uint64) {
-	if !c.Has(SVE) {
-		return 0, 0
-	}
-	return getVectorLength()
-}
-
 // LogicalCPU will return the Logical CPU the code is currently executing on.
 // This is likely to change when the OS re-schedules the running thread
 // to another CPU.
@@ -845,16 +780,11 @@ func threadsPerCore() int {
 	_, b, _, _ := cpuidex(0xb, 0)
 	if b&0xffff == 0 {
 		if vend == AMD {
-			// if >= Zen 2 0x8000001e EBX 15-8 bits means threads per core.
-			// The number of threads per core is ThreadsPerCore+1
-			// See PPR for AMD Family 17h Models 00h-0Fh (page 82)
+			// Workaround for AMD returning 0, assume 2 if >= Zen 2
+			// It will be more correct than not.
 			fam, _, _ := familyModel()
 			_, _, _, d := cpuid(1)
 			if (d&(1<<28)) != 0 && fam >= 23 {
-				if maxExtendedFunction() >= 0x8000001e {
-					_, b, _, _ := cpuid(0x8000001e)
-					return int((b>>8)&0xff) + 1
-				}
 				return 2
 			}
 		}
@@ -917,12 +847,7 @@ func physicalCores() int {
 	v, _ := vendorID()
 	switch v {
 	case Intel:
-		lc := logicalCores()
-		tpc := threadsPerCore()
-		if lc > 0 && tpc > 0 {
-			return lc / tpc
-		}
-		return 0
+		return logicalCores() / threadsPerCore()
 	case AMD, Hygon:
 		lc := logicalCores()
 		tpc := threadsPerCore()
@@ -951,9 +876,7 @@ var vendorMapping = map[string]Vendor{
 	"GenuineTMx86": Transmeta,
 	"Geode by NSC": NSC,
 	"VIA VIA VIA ": VIA,
-	"KVMKVMKVM":    KVM,
-	"Linux KVM Hv": KVM,
-	"TCGTCGTCGTCG": QEMU,
+	"KVMKVMKVMKVM": KVM,
 	"Microsoft Hv": MSVM,
 	"VMwareVMware": VMware,
 	"XenVMMXenVMM": XenHVM,
@@ -963,10 +886,6 @@ var vendorMapping = map[string]Vendor{
 	"SiS SiS SiS ": SiS,
 	"RiseRiseRise": SiS,
 	"Genuine  RDC": RDC,
-	"QNXQVMBSQG":   QNX,
-	"ACRNACRNACRN": ACRN,
-	"SRESRESRESRE": SRE,
-	"Apple VZ":     Apple,
 }

 func vendorID() (Vendor, string) {
@@ -979,17 +898,6 @@ func vendorID() (Vendor, string) {
 	return vend, v
 }

-func hypervisorVendorID() (Vendor, string) {
-	// https://lwn.net/Articles/301888/
-	_, b, c, d := cpuid(0x40000000)
-	v := string(valAsString(b, c, d))
-	vend, ok := vendorMapping[v]
-	if !ok {
-		return VendorUnknown, v
-	}
-	return vend, v
-}
-
 func cacheLine() int {
 	if maxFunctionID() < 0x1 {
 		return 0
@@ -1323,8 +1231,6 @@ func support() flagSet {
 		// CPUID.(EAX=7, ECX=1).EAX
 		eax1, _, _, edx1 := cpuidex(7, 1)
 		fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI)
-		fs.setIf(eax1&(1<<1) != 0, SM3_X86)
-		fs.setIf(eax1&(1<<2) != 0, SM4_X86)
 		fs.setIf(eax1&(1<<7) != 0, CMPCCXADD)
 		fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
 		fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT)
@@ -1336,10 +1242,6 @@ func support() flagSet {
 		// CPUID.(EAX=7, ECX=1).EDX
 		fs.setIf(edx1&(1<<4) != 0, AVXVNNIINT8)
 		fs.setIf(edx1&(1<<5) != 0, AVXNECONVERT)
-		fs.setIf(edx1&(1<<6) != 0, AMXTRANSPOSE)
-		fs.setIf(edx1&(1<<7) != 0, AMXTF32)
-		fs.setIf(edx1&(1<<8) != 0, AMXCOMPLEX)
-		fs.setIf(edx1&(1<<10) != 0, AVXVNNIINT16)
 		fs.setIf(edx1&(1<<14) != 0, PREFETCHI)
 		fs.setIf(edx1&(1<<19) != 0, AVX10)
 		fs.setIf(edx1&(1<<21) != 0, APX_F)
@@ -1367,7 +1269,6 @@ func support() flagSet {
 				fs.setIf(ebx&(1<<31) != 0, AVX512VL)
 				// ecx
 				fs.setIf(ecx&(1<<1) != 0, AVX512VBMI)
-				fs.setIf(ecx&(1<<3) != 0, AMXFP8)
 				fs.setIf(ecx&(1<<6) != 0, AVX512VBMI2)
 				fs.setIf(ecx&(1<<11) != 0, AVX512VNNI)
 				fs.setIf(ecx&(1<<12) != 0, AVX512BITALG)
@@ -1394,11 +1295,6 @@ func support() flagSet {
 		fs.setIf(edx&(1<<4) != 0, BHI_CTRL)
 		fs.setIf(edx&(1<<5) != 0, MCDT_NO)

-		if fs.inSet(SGX) {
-			eax, _, _, _ := cpuidex(0x12, 0)
-			fs.setIf(eax&(1<<12) != 0, SGXPQC)
-		}
-
 		// Add keylocker features.
 		if fs.inSet(KEYLOCKER) && mfi >= 0x19 {
 			_, ebx, _, _ := cpuidex(0x19, 0)
@@ -1412,7 +1308,6 @@ func support() flagSet {
 			fs.setIf(ebx&(1<<17) != 0, AVX10_256)
 			fs.setIf(ebx&(1<<18) != 0, AVX10_512)
 		}
-
 	}

 	// Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
@@ -1556,28 +1451,12 @@ func support() flagSet {
 	}

 	if maxExtendedFunction() >= 0x80000021 && vend == AMD {
-		a, _, c, _ := cpuid(0x80000021)
+		a, _, _, _ := cpuid(0x80000021)
 		fs.setIf((a>>31)&1 == 1, SRSO_MSR_FIX)
 		fs.setIf((a>>30)&1 == 1, SRSO_USER_KERNEL_NO)
 		fs.setIf((a>>29)&1 == 1, SRSO_NO)
 		fs.setIf((a>>28)&1 == 1, IBPB_BRTYPE)
 		fs.setIf((a>>27)&1 == 1, SBPB)
-		fs.setIf((c>>1)&1 == 1, TSA_L1_NO)
-		fs.setIf((c>>2)&1 == 1, TSA_SQ_NO)
-		fs.setIf((a>>5)&1 == 1, TSA_VERW_CLEAR)
-	}
-	if vend == AMD {
-		if family < 0x19 {
-			// AMD CPUs that are older than Family 19h are not vulnerable to TSA but do not set TSA_L1_NO or TSA_SQ_NO.
-			// Source: https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf
-			fs.set(TSA_L1_NO)
-			fs.set(TSA_SQ_NO)
-		} else if family == 0x1a {
-			// AMD Family 1Ah models 00h-4Fh and 60h-7Fh are also not vulnerable to TSA but do not set TSA_L1_NO or TSA_SQ_NO.
-			// Future AMD CPUs will set these CPUID bits if appropriate. CPUs will be designed to set these CPUID bits if appropriate.
-			notVuln := model <= 0x4f || (model >= 0x60 && model <= 0x7f)
-			fs.setIf(notVuln, TSA_L1_NO, TSA_SQ_NO)
-		}
 	}

 	if mfi >= 0x20 {
@@ -1633,47 +1512,3 @@ func valAsString(values ...uint32) []byte {
 	}
 	return r
 }
-
-func parseLeaf0AH(c *CPUInfo, eax, ebx, edx uint32) (info PerformanceMonitoringInfo) {
-	info.VersionID = uint8(eax & 0xFF)
-	info.NumGPCounters = uint8((eax >> 8) & 0xFF)
-	info.GPPMCWidth = uint8((eax >> 16) & 0xFF)
-
-	info.RawEBX = ebx
-	info.RawEAX = eax
-	info.RawEDX = edx
-
-	if info.VersionID > 1 { // This information is only valid if VersionID > 1
-		info.NumFixedPMC = uint8(edx & 0x1F)          // Bits 4:0
-		info.FixedPMCWidth = uint8((edx >> 5) & 0xFF) // Bits 12:5
-	}
-	if info.VersionID > 0 {
-		// first 4 fixed events are always instructions retired, cycles, ref cycles and topdown slots
-		if ebx == 0x0 && info.NumFixedPMC == 3 {
-			c.featureSet.set(PMU_FIXEDCOUNTER_INSTRUCTIONS)
-			c.featureSet.set(PMU_FIXEDCOUNTER_CYCLES)
-			c.featureSet.set(PMU_FIXEDCOUNTER_REFCYCLES)
-		}
-		if ebx == 0x0 && info.NumFixedPMC == 4 {
-			c.featureSet.set(PMU_FIXEDCOUNTER_INSTRUCTIONS)
-			c.featureSet.set(PMU_FIXEDCOUNTER_CYCLES)
-			c.featureSet.set(PMU_FIXEDCOUNTER_REFCYCLES)
-			c.featureSet.set(PMU_FIXEDCOUNTER_TOPDOWN_SLOTS)
-		}
-		if ebx != 0x0 {
-			if ((ebx >> 0) & 1) == 0 {
-				c.featureSet.set(PMU_FIXEDCOUNTER_INSTRUCTIONS)
-			}
-			if ((ebx >> 1) & 1) == 0 {
-				c.featureSet.set(PMU_FIXEDCOUNTER_CYCLES)
-			}
-			if ((ebx >> 2) & 1) == 0 {
-				c.featureSet.set(PMU_FIXEDCOUNTER_REFCYCLES)
-			}
-			if ((ebx >> 3) & 1) == 0 {
-				c.featureSet.set(PMU_FIXEDCOUNTER_TOPDOWN_SLOTS)
-			}
-		}
-	}
-	return info
-}
--- a/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s
+++ b/vendor/github.com/klauspost/cpuid/v2/cpuid_arm64.s
@@ -24,13 +24,3 @@ TEXT ·getInstAttributes(SB), 7, $0
 	MOVD R1, instAttrReg1+8(FP)
 	RET

-TEXT ·getVectorLength(SB), 7, $0
-	WORD $0xd2800002  // mov   x2, #0
-	WORD $0x04225022  // addvl x2, x2, #1
-	WORD $0xd37df042  // lsl   x2, x2, #3
-	WORD $0xd2800003  // mov   x3, #0
-	WORD $0x04635023  // addpl x3, x3, #1
-	WORD $0xd37df063  // lsl   x3, x3, #3
-	MOVD R2, vl+0(FP)
-	MOVD R3, pl+8(FP)
-	RET
--- a/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_arm64.go
@@ -10,7 +10,6 @@ import "runtime"
 func getMidr() (midr uint64)
 func getProcFeatures() (procFeatures uint64)
 func getInstAttributes() (instAttrReg0, instAttrReg1 uint64)
-func getVectorLength() (vl, pl uint64)

 func initCPU() {
 	cpuid = func(uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
@@ -25,7 +24,7 @@ func addInfo(c *CPUInfo, safe bool) {
 	detectOS(c)

 	// ARM64 disabled since it may crash if interrupt is not intercepted by OS.
-	if safe && !c.Has(ARMCPUID) && runtime.GOOS != "freebsd" {
+	if safe && !c.Supports(ARMCPUID) && runtime.GOOS != "freebsd" {
 		return
 	}
 	midr := getMidr()
@@ -157,10 +156,6 @@ func addInfo(c *CPUInfo, safe bool) {
 	// x--------------------------------------------------x
 	// | Name                         |  bits   | visible |
 	// |--------------------------------------------------|
-	// | RNDR                         | [63-60] |    y    |
-	// |--------------------------------------------------|
-	// | TLB                          | [59-56] |    y    |
-	// |--------------------------------------------------|
 	// | TS                           | [55-52] |    y    |
 	// |--------------------------------------------------|
 	// | FHM                          | [51-48] |    y    |
@@ -186,10 +181,12 @@ func addInfo(c *CPUInfo, safe bool) {
 	// | AES                          | [7-4]   |    y    |
 	// x--------------------------------------------------x

-	f.setIf(instAttrReg0&(0xf<<60) != 0, RNDR)
-	f.setIf(instAttrReg0&(0xf<<56) != 0, TLB)
-	f.setIf(instAttrReg0&(0xf<<52) != 0, TS)
-	f.setIf(instAttrReg0&(0xf<<48) != 0, FHM)
+	// if instAttrReg0&(0xf<<52) != 0 {
+	// 	fmt.Println("TS")
+	// }
+	// if instAttrReg0&(0xf<<48) != 0 {
+	// 	fmt.Println("FHM")
+	// }
 	f.setIf(instAttrReg0&(0xf<<44) != 0, ASIMDDP)
 	f.setIf(instAttrReg0&(0xf<<40) != 0, SM4)
 	f.setIf(instAttrReg0&(0xf<<36) != 0, SM3)
--- a/vendor/github.com/klauspost/cpuid/v2/detect_ref.go
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_ref.go
@@ -10,8 +10,6 @@ func initCPU() {
 	cpuidex = func(x, y uint32) (a, b, c, d uint32) { return 0, 0, 0, 0 }
 	xgetbv = func(uint32) (a, b uint32) { return 0, 0 }
 	rdtscpAsm = func() (a, b, c, d uint32) { return 0, 0, 0, 0 }
-
 }

 func addInfo(info *CPUInfo, safe bool) {}
-func getVectorLength() (vl, pl uint64) { return 0, 0 }
--- a/vendor/github.com/klauspost/cpuid/v2/detect_x86.go
+++ b/vendor/github.com/klauspost/cpuid/v2/detect_x86.go
@@ -32,14 +32,7 @@ func addInfo(c *CPUInfo, safe bool) {
 	c.LogicalCores = logicalCores()
 	c.PhysicalCores = physicalCores()
 	c.VendorID, c.VendorString = vendorID()
-	c.HypervisorVendorID, c.HypervisorVendorString = hypervisorVendorID()
 	c.AVX10Level = c.supportAVX10()
 	c.cacheSize()
 	c.frequencies()
-	if c.maxFunc >= 0x0A {
-		eax, ebx, _, edx := cpuid(0x0A)
-		c.PMU = parseLeaf0AH(c, eax, ebx, edx)
-	}
 }
-
-func getVectorLength() (vl, pl uint64) { return 0, 0 }
--- a/vendor/github.com/klauspost/cpuid/v2/featureid_string.go
+++ b/vendor/github.com/klauspost/cpuid/v2/featureid_string.go
@@ -15,242 +15,223 @@ func _() {
 	_ = x[AMXBF16-5]
 	_ = x[AMXFP16-6]
 	_ = x[AMXINT8-7]
-	_ = x[AMXFP8-8]
-	_ = x[AMXTILE-9]
-	_ = x[AMXTF32-10]
-	_ = x[AMXCOMPLEX-11]
-	_ = x[AMXTRANSPOSE-12]
-	_ = x[APX_F-13]
-	_ = x[AVX-14]
-	_ = x[AVX10-15]
-	_ = x[AVX10_128-16]
-	_ = x[AVX10_256-17]
-	_ = x[AVX10_512-18]
-	_ = x[AVX2-19]
-	_ = x[AVX512BF16-20]
-	_ = x[AVX512BITALG-21]
-	_ = x[AVX512BW-22]
-	_ = x[AVX512CD-23]
-	_ = x[AVX512DQ-24]
-	_ = x[AVX512ER-25]
-	_ = x[AVX512F-26]
-	_ = x[AVX512FP16-27]
-	_ = x[AVX512IFMA-28]
-	_ = x[AVX512PF-29]
-	_ = x[AVX512VBMI-30]
-	_ = x[AVX512VBMI2-31]
-	_ = x[AVX512VL-32]
-	_ = x[AVX512VNNI-33]
-	_ = x[AVX512VP2INTERSECT-34]
-	_ = x[AVX512VPOPCNTDQ-35]
-	_ = x[AVXIFMA-36]
-	_ = x[AVXNECONVERT-37]
-	_ = x[AVXSLOW-38]
-	_ = x[AVXVNNI-39]
-	_ = x[AVXVNNIINT8-40]
-	_ = x[AVXVNNIINT16-41]
-	_ = x[BHI_CTRL-42]
-	_ = x[BMI1-43]
-	_ = x[BMI2-44]
-	_ = x[CETIBT-45]
-	_ = x[CETSS-46]
-	_ = x[CLDEMOTE-47]
-	_ = x[CLMUL-48]
-	_ = x[CLZERO-49]
-	_ = x[CMOV-50]
-	_ = x[CMPCCXADD-51]
-	_ = x[CMPSB_SCADBS_SHORT-52]
-	_ = x[CMPXCHG8-53]
-	_ = x[CPBOOST-54]
-	_ = x[CPPC-55]
-	_ = x[CX16-56]
-	_ = x[EFER_LMSLE_UNS-57]
-	_ = x[ENQCMD-58]
-	_ = x[ERMS-59]
-	_ = x[F16C-60]
-	_ = x[FLUSH_L1D-61]
-	_ = x[FMA3-62]
-	_ = x[FMA4-63]
-	_ = x[FP128-64]
-	_ = x[FP256-65]
-	_ = x[FSRM-66]
-	_ = x[FXSR-67]
-	_ = x[FXSROPT-68]
-	_ = x[GFNI-69]
-	_ = x[HLE-70]
-	_ = x[HRESET-71]
-	_ = x[HTT-72]
-	_ = x[HWA-73]
-	_ = x[HYBRID_CPU-74]
-	_ = x[HYPERVISOR-75]
-	_ = x[IA32_ARCH_CAP-76]
-	_ = x[IA32_CORE_CAP-77]
-	_ = x[IBPB-78]
-	_ = x[IBPB_BRTYPE-79]
-	_ = x[IBRS-80]
-	_ = x[IBRS_PREFERRED-81]
-	_ = x[IBRS_PROVIDES_SMP-82]
-	_ = x[IBS-83]
-	_ = x[IBSBRNTRGT-84]
-	_ = x[IBSFETCHSAM-85]
-	_ = x[IBSFFV-86]
-	_ = x[IBSOPCNT-87]
-	_ = x[IBSOPCNTEXT-88]
-	_ = x[IBSOPSAM-89]
-	_ = x[IBSRDWROPCNT-90]
-	_ = x[IBSRIPINVALIDCHK-91]
-	_ = x[IBS_FETCH_CTLX-92]
-	_ = x[IBS_OPDATA4-93]
-	_ = x[IBS_OPFUSE-94]
-	_ = x[IBS_PREVENTHOST-95]
-	_ = x[IBS_ZEN4-96]
-	_ = x[IDPRED_CTRL-97]
-	_ = x[INT_WBINVD-98]
-	_ = x[INVLPGB-99]
-	_ = x[KEYLOCKER-100]
-	_ = x[KEYLOCKERW-101]
-	_ = x[LAHF-102]
-	_ = x[LAM-103]
-	_ = x[LBRVIRT-104]
-	_ = x[LZCNT-105]
-	_ = x[MCAOVERFLOW-106]
-	_ = x[MCDT_NO-107]
-	_ = x[MCOMMIT-108]
-	_ = x[MD_CLEAR-109]
-	_ = x[MMX-110]
-	_ = x[MMXEXT-111]
-	_ = x[MOVBE-112]
-	_ = x[MOVDIR64B-113]
-	_ = x[MOVDIRI-114]
-	_ = x[MOVSB_ZL-115]
-	_ = x[MOVU-116]
-	_ = x[MPX-117]
-	_ = x[MSRIRC-118]
-	_ = x[MSRLIST-119]
-	_ = x[MSR_PAGEFLUSH-120]
-	_ = x[NRIPS-121]
-	_ = x[NX-122]
-	_ = x[OSXSAVE-123]
-	_ = x[PCONFIG-124]
-	_ = x[POPCNT-125]
-	_ = x[PPIN-126]
-	_ = x[PREFETCHI-127]
-	_ = x[PSFD-128]
-	_ = x[RDPRU-129]
-	_ = x[RDRAND-130]
-	_ = x[RDSEED-131]
-	_ = x[RDTSCP-132]
-	_ = x[RRSBA_CTRL-133]
-	_ = x[RTM-134]
-	_ = x[RTM_ALWAYS_ABORT-135]
-	_ = x[SBPB-136]
-	_ = x[SERIALIZE-137]
-	_ = x[SEV-138]
-	_ = x[SEV_64BIT-139]
-	_ = x[SEV_ALTERNATIVE-140]
-	_ = x[SEV_DEBUGSWAP-141]
-	_ = x[SEV_ES-142]
-	_ = x[SEV_RESTRICTED-143]
-	_ = x[SEV_SNP-144]
-	_ = x[SGX-145]
-	_ = x[SGXLC-146]
-	_ = x[SGXPQC-147]
-	_ = x[SHA-148]
-	_ = x[SME-149]
-	_ = x[SME_COHERENT-150]
-	_ = x[SM3_X86-151]
-	_ = x[SM4_X86-152]
-	_ = x[SPEC_CTRL_SSBD-153]
-	_ = x[SRBDS_CTRL-154]
-	_ = x[SRSO_MSR_FIX-155]
-	_ = x[SRSO_NO-156]
-	_ = x[SRSO_USER_KERNEL_NO-157]
-	_ = x[SSE-158]
-	_ = x[SSE2-159]
-	_ = x[SSE3-160]
-	_ = x[SSE4-161]
-	_ = x[SSE42-162]
-	_ = x[SSE4A-163]
-	_ = x[SSSE3-164]
-	_ = x[STIBP-165]
-	_ = x[STIBP_ALWAYSON-166]
-	_ = x[STOSB_SHORT-167]
-	_ = x[SUCCOR-168]
-	_ = x[SVM-169]
-	_ = x[SVMDA-170]
-	_ = x[SVMFBASID-171]
-	_ = x[SVML-172]
-	_ = x[SVMNP-173]
-	_ = x[SVMPF-174]
-	_ = x[SVMPFT-175]
-	_ = x[SYSCALL-176]
-	_ = x[SYSEE-177]
-	_ = x[TBM-178]
-	_ = x[TDX_GUEST-179]
-	_ = x[TLB_FLUSH_NESTED-180]
-	_ = x[TME-181]
-	_ = x[TOPEXT-182]
-	_ = x[TSA_L1_NO-183]
-	_ = x[TSA_SQ_NO-184]
-	_ = x[TSA_VERW_CLEAR-185]
-	_ = x[TSCRATEMSR-186]
-	_ = x[TSXLDTRK-187]
-	_ = x[VAES-188]
-	_ = x[VMCBCLEAN-189]
-	_ = x[VMPL-190]
-	_ = x[VMSA_REGPROT-191]
-	_ = x[VMX-192]
-	_ = x[VPCLMULQDQ-193]
-	_ = x[VTE-194]
-	_ = x[WAITPKG-195]
-	_ = x[WBNOINVD-196]
-	_ = x[WRMSRNS-197]
-	_ = x[X87-198]
-	_ = x[XGETBV1-199]
-	_ = x[XOP-200]
-	_ = x[XSAVE-201]
-	_ = x[XSAVEC-202]
-	_ = x[XSAVEOPT-203]
-	_ = x[XSAVES-204]
-	_ = x[AESARM-205]
-	_ = x[ARMCPUID-206]
-	_ = x[ASIMD-207]
-	_ = x[ASIMDDP-208]
-	_ = x[ASIMDHP-209]
-	_ = x[ASIMDRDM-210]
-	_ = x[ATOMICS-211]
-	_ = x[CRC32-212]
-	_ = x[DCPOP-213]
-	_ = x[EVTSTRM-214]
-	_ = x[FCMA-215]
-	_ = x[FHM-216]
-	_ = x[FP-217]
-	_ = x[FPHP-218]
-	_ = x[GPA-219]
-	_ = x[JSCVT-220]
-	_ = x[LRCPC-221]
-	_ = x[PMULL-222]
-	_ = x[RNDR-223]
-	_ = x[TLB-224]
-	_ = x[TS-225]
-	_ = x[SHA1-226]
-	_ = x[SHA2-227]
-	_ = x[SHA3-228]
-	_ = x[SHA512-229]
-	_ = x[SM3-230]
-	_ = x[SM4-231]
-	_ = x[SVE-232]
-	_ = x[PMU_FIXEDCOUNTER_CYCLES-233]
-	_ = x[PMU_FIXEDCOUNTER_REFCYCLES-234]
-	_ = x[PMU_FIXEDCOUNTER_INSTRUCTIONS-235]
-	_ = x[PMU_FIXEDCOUNTER_TOPDOWN_SLOTS-236]
-	_ = x[lastID-237]
+	_ = x[AMXTILE-8]
+	_ = x[APX_F-9]
+	_ = x[AVX-10]
+	_ = x[AVX10-11]
+	_ = x[AVX10_128-12]
+	_ = x[AVX10_256-13]
+	_ = x[AVX10_512-14]
+	_ = x[AVX2-15]
+	_ = x[AVX512BF16-16]
+	_ = x[AVX512BITALG-17]
+	_ = x[AVX512BW-18]
+	_ = x[AVX512CD-19]
+	_ = x[AVX512DQ-20]
+	_ = x[AVX512ER-21]
+	_ = x[AVX512F-22]
+	_ = x[AVX512FP16-23]
+	_ = x[AVX512IFMA-24]
+	_ = x[AVX512PF-25]
+	_ = x[AVX512VBMI-26]
+	_ = x[AVX512VBMI2-27]
+	_ = x[AVX512VL-28]
+	_ = x[AVX512VNNI-29]
+	_ = x[AVX512VP2INTERSECT-30]
+	_ = x[AVX512VPOPCNTDQ-31]
+	_ = x[AVXIFMA-32]
+	_ = x[AVXNECONVERT-33]
+	_ = x[AVXSLOW-34]
+	_ = x[AVXVNNI-35]
+	_ = x[AVXVNNIINT8-36]
+	_ = x[BHI_CTRL-37]
+	_ = x[BMI1-38]
+	_ = x[BMI2-39]
+	_ = x[CETIBT-40]
+	_ = x[CETSS-41]
+	_ = x[CLDEMOTE-42]
+	_ = x[CLMUL-43]
+	_ = x[CLZERO-44]
+	_ = x[CMOV-45]
+	_ = x[CMPCCXADD-46]
+	_ = x[CMPSB_SCADBS_SHORT-47]
+	_ = x[CMPXCHG8-48]
+	_ = x[CPBOOST-49]
+	_ = x[CPPC-50]
+	_ = x[CX16-51]
+	_ = x[EFER_LMSLE_UNS-52]
+	_ = x[ENQCMD-53]
+	_ = x[ERMS-54]
+	_ = x[F16C-55]
+	_ = x[FLUSH_L1D-56]
+	_ = x[FMA3-57]
+	_ = x[FMA4-58]
+	_ = x[FP128-59]
+	_ = x[FP256-60]
+	_ = x[FSRM-61]
+	_ = x[FXSR-62]
+	_ = x[FXSROPT-63]
+	_ = x[GFNI-64]
+	_ = x[HLE-65]
+	_ = x[HRESET-66]
+	_ = x[HTT-67]
+	_ = x[HWA-68]
+	_ = x[HYBRID_CPU-69]
+	_ = x[HYPERVISOR-70]
+	_ = x[IA32_ARCH_CAP-71]
+	_ = x[IA32_CORE_CAP-72]
+	_ = x[IBPB-73]
+	_ = x[IBPB_BRTYPE-74]
+	_ = x[IBRS-75]
+	_ = x[IBRS_PREFERRED-76]
+	_ = x[IBRS_PROVIDES_SMP-77]
+	_ = x[IBS-78]
+	_ = x[IBSBRNTRGT-79]
+	_ = x[IBSFETCHSAM-80]
+	_ = x[IBSFFV-81]
+	_ = x[IBSOPCNT-82]
+	_ = x[IBSOPCNTEXT-83]
+	_ = x[IBSOPSAM-84]
+	_ = x[IBSRDWROPCNT-85]
+	_ = x[IBSRIPINVALIDCHK-86]
+	_ = x[IBS_FETCH_CTLX-87]
+	_ = x[IBS_OPDATA4-88]
+	_ = x[IBS_OPFUSE-89]
+	_ = x[IBS_PREVENTHOST-90]
+	_ = x[IBS_ZEN4-91]
+	_ = x[IDPRED_CTRL-92]
+	_ = x[INT_WBINVD-93]
+	_ = x[INVLPGB-94]
+	_ = x[KEYLOCKER-95]
+	_ = x[KEYLOCKERW-96]
+	_ = x[LAHF-97]
+	_ = x[LAM-98]
+	_ = x[LBRVIRT-99]
+	_ = x[LZCNT-100]
+	_ = x[MCAOVERFLOW-101]
+	_ = x[MCDT_NO-102]
+	_ = x[MCOMMIT-103]
+	_ = x[MD_CLEAR-104]
+	_ = x[MMX-105]
+	_ = x[MMXEXT-106]
+	_ = x[MOVBE-107]
+	_ = x[MOVDIR64B-108]
+	_ = x[MOVDIRI-109]
+	_ = x[MOVSB_ZL-110]
+	_ = x[MOVU-111]
+	_ = x[MPX-112]
+	_ = x[MSRIRC-113]
+	_ = x[MSRLIST-114]
+	_ = x[MSR_PAGEFLUSH-115]
+	_ = x[NRIPS-116]
+	_ = x[NX-117]
+	_ = x[OSXSAVE-118]
+	_ = x[PCONFIG-119]
+	_ = x[POPCNT-120]
+	_ = x[PPIN-121]
+	_ = x[PREFETCHI-122]
+	_ = x[PSFD-123]
+	_ = x[RDPRU-124]
+	_ = x[RDRAND-125]
+	_ = x[RDSEED-126]
+	_ = x[RDTSCP-127]
+	_ = x[RRSBA_CTRL-128]
+	_ = x[RTM-129]
+	_ = x[RTM_ALWAYS_ABORT-130]
+	_ = x[SBPB-131]
+	_ = x[SERIALIZE-132]
+	_ = x[SEV-133]
+	_ = x[SEV_64BIT-134]
+	_ = x[SEV_ALTERNATIVE-135]
+	_ = x[SEV_DEBUGSWAP-136]
+	_ = x[SEV_ES-137]
+	_ = x[SEV_RESTRICTED-138]
+	_ = x[SEV_SNP-139]
+	_ = x[SGX-140]
+	_ = x[SGXLC-141]
+	_ = x[SHA-142]
+	_ = x[SME-143]
+	_ = x[SME_COHERENT-144]
+	_ = x[SPEC_CTRL_SSBD-145]
+	_ = x[SRBDS_CTRL-146]
+	_ = x[SRSO_MSR_FIX-147]
+	_ = x[SRSO_NO-148]
+	_ = x[SRSO_USER_KERNEL_NO-149]
+	_ = x[SSE-150]
+	_ = x[SSE2-151]
+	_ = x[SSE3-152]
+	_ = x[SSE4-153]
+	_ = x[SSE42-154]
+	_ = x[SSE4A-155]
+	_ = x[SSSE3-156]
+	_ = x[STIBP-157]
+	_ = x[STIBP_ALWAYSON-158]
+	_ = x[STOSB_SHORT-159]
+	_ = x[SUCCOR-160]
+	_ = x[SVM-161]
+	_ = x[SVMDA-162]
+	_ = x[SVMFBASID-163]
+	_ = x[SVML-164]
+	_ = x[SVMNP-165]
+	_ = x[SVMPF-166]
+	_ = x[SVMPFT-167]
+	_ = x[SYSCALL-168]
+	_ = x[SYSEE-169]
+	_ = x[TBM-170]
+	_ = x[TDX_GUEST-171]
+	_ = x[TLB_FLUSH_NESTED-172]
+	_ = x[TME-173]
+	_ = x[TOPEXT-174]
+	_ = x[TSCRATEMSR-175]
+	_ = x[TSXLDTRK-176]
+	_ = x[VAES-177]
+	_ = x[VMCBCLEAN-178]
+	_ = x[VMPL-179]
+	_ = x[VMSA_REGPROT-180]
+	_ = x[VMX-181]
+	_ = x[VPCLMULQDQ-182]
+	_ = x[VTE-183]
+	_ = x[WAITPKG-184]
+	_ = x[WBNOINVD-185]
+	_ = x[WRMSRNS-186]
+	_ = x[X87-187]
+	_ = x[XGETBV1-188]
+	_ = x[XOP-189]
+	_ = x[XSAVE-190]
+	_ = x[XSAVEC-191]
+	_ = x[XSAVEOPT-192]
+	_ = x[XSAVES-193]
+	_ = x[AESARM-194]
+	_ = x[ARMCPUID-195]
+	_ = x[ASIMD-196]
+	_ = x[ASIMDDP-197]
+	_ = x[ASIMDHP-198]
+	_ = x[ASIMDRDM-199]
+	_ = x[ATOMICS-200]
+	_ = x[CRC32-201]
+	_ = x[DCPOP-202]
+	_ = x[EVTSTRM-203]
+	_ = x[FCMA-204]
+	_ = x[FP-205]
+	_ = x[FPHP-206]
+	_ = x[GPA-207]
+	_ = x[JSCVT-208]
+	_ = x[LRCPC-209]
+	_ = x[PMULL-210]
+	_ = x[SHA1-211]
+	_ = x[SHA2-212]
+	_ = x[SHA3-213]
+	_ = x[SHA512-214]
+	_ = x[SM3-215]
+	_ = x[SM4-216]
+	_ = x[SVE-217]
+	_ = x[lastID-218]
 	_ = x[firstID-0]
 }

-const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXFP8AMXTILEAMXTF32AMXCOMPLEXAMXTRANSPOSEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8AVXVNNIINT16BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSGXPQCSHASMESME_COHERENTSM3_X86SM4_X86SPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSA_L1_NOTSA_SQ_NOTSA_VERW_CLEARTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFHMFPFPHPGPAJSCVTLRCPCPMULLRNDRTLBTSSHA1SHA2SHA3SHA512SM3SM4SVEPMU_FIXEDCOUNTER_CYCLESPMU_FIXEDCOUNTER_REFCYCLESPMU_FIXEDCOUNTER_INSTRUCTIONSPMU_FIXEDCOUNTER_TOPDOWN_SLOTSlastID"
+const _FeatureID_name = "firstIDADXAESNIAMD3DNOWAMD3DNOWEXTAMXBF16AMXFP16AMXINT8AMXTILEAPX_FAVXAVX10AVX10_128AVX10_256AVX10_512AVX2AVX512BF16AVX512BITALGAVX512BWAVX512CDAVX512DQAVX512ERAVX512FAVX512FP16AVX512IFMAAVX512PFAVX512VBMIAVX512VBMI2AVX512VLAVX512VNNIAVX512VP2INTERSECTAVX512VPOPCNTDQAVXIFMAAVXNECONVERTAVXSLOWAVXVNNIAVXVNNIINT8BHI_CTRLBMI1BMI2CETIBTCETSSCLDEMOTECLMULCLZEROCMOVCMPCCXADDCMPSB_SCADBS_SHORTCMPXCHG8CPBOOSTCPPCCX16EFER_LMSLE_UNSENQCMDERMSF16CFLUSH_L1DFMA3FMA4FP128FP256FSRMFXSRFXSROPTGFNIHLEHRESETHTTHWAHYBRID_CPUHYPERVISORIA32_ARCH_CAPIA32_CORE_CAPIBPBIBPB_BRTYPEIBRSIBRS_PREFERREDIBRS_PROVIDES_SMPIBSIBSBRNTRGTIBSFETCHSAMIBSFFVIBSOPCNTIBSOPCNTEXTIBSOPSAMIBSRDWROPCNTIBSRIPINVALIDCHKIBS_FETCH_CTLXIBS_OPDATA4IBS_OPFUSEIBS_PREVENTHOSTIBS_ZEN4IDPRED_CTRLINT_WBINVDINVLPGBKEYLOCKERKEYLOCKERWLAHFLAMLBRVIRTLZCNTMCAOVERFLOWMCDT_NOMCOMMITMD_CLEARMMXMMXEXTMOVBEMOVDIR64BMOVDIRIMOVSB_ZLMOVUMPXMSRIRCMSRLISTMSR_PAGEFLUSHNRIPSNXOSXSAVEPCONFIGPOPCNTPPINPREFETCHIPSFDRDPRURDRANDRDSEEDRDTSCPRRSBA_CTRLRTMRTM_ALWAYS_ABORTSBPBSERIALIZESEVSEV_64BITSEV_ALTERNATIVESEV_DEBUGSWAPSEV_ESSEV_RESTRICTEDSEV_SNPSGXSGXLCSHASMESME_COHERENTSPEC_CTRL_SSBDSRBDS_CTRLSRSO_MSR_FIXSRSO_NOSRSO_USER_KERNEL_NOSSESSE2SSE3SSE4SSE42SSE4ASSSE3STIBPSTIBP_ALWAYSONSTOSB_SHORTSUCCORSVMSVMDASVMFBASIDSVMLSVMNPSVMPFSVMPFTSYSCALLSYSEETBMTDX_GUESTTLB_FLUSH_NESTEDTMETOPEXTTSCRATEMSRTSXLDTRKVAESVMCBCLEANVMPLVMSA_REGPROTVMXVPCLMULQDQVTEWAITPKGWBNOINVDWRMSRNSX87XGETBV1XOPXSAVEXSAVECXSAVEOPTXSAVESAESARMARMCPUIDASIMDASIMDDPASIMDHPASIMDRDMATOMICSCRC32DCPOPEVTSTRMFCMAFPFPHPGPAJSCVTLRCPCPMULLSHA1SHA2SHA3SHA512SM3SM4SVElastID"

-var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 61, 68, 75, 85, 97, 102, 105, 110, 119, 128, 137, 141, 151, 163, 171, 179, 187, 195, 202, 212, 222, 230, 240, 251, 259, 269, 287, 302, 309, 321, 328, 335, 346, 358, 366, 370, 374, 380, 385, 393, 398, 404, 408, 417, 435, 443, 450, 454, 458, 472, 478, 482, 486, 495, 499, 503, 508, 513, 517, 521, 528, 532, 535, 541, 544, 547, 557, 567, 580, 593, 597, 608, 612, 626, 643, 646, 656, 667, 673, 681, 692, 700, 712, 728, 742, 753, 763, 778, 786, 797, 807, 814, 823, 833, 837, 840, 847, 852, 863, 870, 877, 885, 888, 894, 899, 908, 915, 923, 927, 930, 936, 943, 956, 961, 963, 970, 977, 983, 987, 996, 1000, 1005, 1011, 1017, 1023, 1033, 1036, 1052, 1056, 1065, 1068, 1077, 1092, 1105, 1111, 1125, 1132, 1135, 1140, 1146, 1149, 1152, 1164, 1171, 1178, 1192, 1202, 1214, 1221, 1240, 1243, 1247, 1251, 1255, 1260, 1265, 1270, 1275, 1289, 1300, 1306, 1309, 1314, 1323, 1327, 1332, 1337, 1343, 1350, 1355, 1358, 1367, 1383, 1386, 1392, 1401, 1410, 1424, 1434, 1442, 1446, 1455, 1459, 1471, 1474, 1484, 1487, 1494, 1502, 1509, 1512, 1519, 1522, 1527, 1533, 1541, 1547, 1553, 1561, 1566, 1573, 1580, 1588, 1595, 1600, 1605, 1612, 1616, 1619, 1621, 1625, 1628, 1633, 1638, 1643, 1647, 1650, 1652, 1656, 1660, 1664, 1670, 1673, 1676, 1679, 1702, 1728, 1757, 1787, 1793}
+var _FeatureID_index = [...]uint16{0, 7, 10, 15, 23, 34, 41, 48, 55, 62, 67, 70, 75, 84, 93, 102, 106, 116, 128, 136, 144, 152, 160, 167, 177, 187, 195, 205, 216, 224, 234, 252, 267, 274, 286, 293, 300, 311, 319, 323, 327, 333, 338, 346, 351, 357, 361, 370, 388, 396, 403, 407, 411, 425, 431, 435, 439, 448, 452, 456, 461, 466, 470, 474, 481, 485, 488, 494, 497, 500, 510, 520, 533, 546, 550, 561, 565, 579, 596, 599, 609, 620, 626, 634, 645, 653, 665, 681, 695, 706, 716, 731, 739, 750, 760, 767, 776, 786, 790, 793, 800, 805, 816, 823, 830, 838, 841, 847, 852, 861, 868, 876, 880, 883, 889, 896, 909, 914, 916, 923, 930, 936, 940, 949, 953, 958, 964, 970, 976, 986, 989, 1005, 1009, 1018, 1021, 1030, 1045, 1058, 1064, 1078, 1085, 1088, 1093, 1096, 1099, 1111, 1125, 1135, 1147, 1154, 1173, 1176, 1180, 1184, 1188, 1193, 1198, 1203, 1208, 1222, 1233, 1239, 1242, 1247, 1256, 1260, 1265, 1270, 1276, 1283, 1288, 1291, 1300, 1316, 1319, 1325, 1335, 1343, 1347, 1356, 1360, 1372, 1375, 1385, 1388, 1395, 1403, 1410, 1413, 1420, 1423, 1428, 1434, 1442, 1448, 1454, 1462, 1467, 1474, 1481, 1489, 1496, 1501, 1506, 1513, 1517, 1519, 1523, 1526, 1531, 1536, 1541, 1545, 1549, 1553, 1559, 1562, 1565, 1568, 1574}

 func (i FeatureID) String() string {
 	if i < 0 || i >= FeatureID(len(_FeatureID_index)-1) {
@@ -288,17 +269,12 @@ func _() {
 	_ = x[AMCC-23]
 	_ = x[Qualcomm-24]
 	_ = x[Marvell-25]
-	_ = x[QEMU-26]
-	_ = x[QNX-27]
-	_ = x[ACRN-28]
-	_ = x[SRE-29]
-	_ = x[Apple-30]
-	_ = x[lastVendor-31]
+	_ = x[lastVendor-26]
 }

-const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvellQEMUQNXACRNSREApplelastVendor"
+const _Vendor_name = "VendorUnknownIntelAMDVIATransmetaNSCKVMMSVMVMwareXenHVMBhyveHygonSiSRDCAmpereARMBroadcomCaviumDECFujitsuInfineonMotorolaNVIDIAAMCCQualcommMarvelllastVendor"

-var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 149, 152, 156, 159, 164, 174}
+var _Vendor_index = [...]uint8{0, 13, 18, 21, 24, 33, 36, 39, 43, 49, 55, 60, 65, 68, 71, 77, 80, 88, 94, 97, 104, 112, 120, 126, 130, 138, 145, 155}

 func (i Vendor) String() string {
 	if i < 0 || i >= Vendor(len(_Vendor_index)-1) {
--- a/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_darwin_arm64.go
@@ -65,16 +65,9 @@ func sysctlGetInt64(unknown int, names ...string) int {
 	return unknown
 }

-func setFeature(c *CPUInfo, feature FeatureID, aliases ...string) {
-	for _, alias := range aliases {
-		set := sysctlGetBool(alias)
-		c.featureSet.setIf(set, feature)
-		if set {
-			break
-		}
-	}
+func setFeature(c *CPUInfo, name string, feature FeatureID) {
+	c.featureSet.setIf(sysctlGetBool(name), feature)
 }
-
 func tryToFillCPUInfoFomSysctl(c *CPUInfo) {
 	c.BrandName = sysctlGetString("machdep.cpu.brand_string")

@@ -94,36 +87,35 @@ func tryToFillCPUInfoFomSysctl(c *CPUInfo) {
 	c.Cache.L2 = sysctlGetInt64(-1, "hw.l2cachesize")
 	c.Cache.L3 = sysctlGetInt64(-1, "hw.l3cachesize")

-	// ARM features:
-	//
-	// Note: On some Apple Silicon system, some feats have aliases. See:
-	// https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics
-	// When so, we look at all aliases and consider a feature available when at least one identifier matches.
-	setFeature(c, AESARM, "hw.optional.arm.FEAT_AES")                                   // AES instructions
-	setFeature(c, ASIMD, "hw.optional.arm.AdvSIMD", "hw.optional.neon")                 // Advanced SIMD
-	setFeature(c, ASIMDDP, "hw.optional.arm.FEAT_DotProd")                              // SIMD Dot Product
-	setFeature(c, ASIMDHP, "hw.optional.arm.AdvSIMD_HPFPCvt", "hw.optional.neon_hpfp")  // Advanced SIMD half-precision floating point
-	setFeature(c, ASIMDRDM, "hw.optional.arm.FEAT_RDM")                                 // Rounding Double Multiply Accumulate/Subtract
-	setFeature(c, ATOMICS, "hw.optional.arm.FEAT_LSE", "hw.optional.armv8_1_atomics")   // Large System Extensions (LSE)
-	setFeature(c, CRC32, "hw.optional.arm.FEAT_CRC32", "hw.optional.armv8_crc32")       // CRC32/CRC32C instructions
-	setFeature(c, DCPOP, "hw.optional.arm.FEAT_DPB")                                    // Data cache clean to Point of Persistence (DC CVAP)
-	setFeature(c, EVTSTRM, "hw.optional.arm.FEAT_ECV")                                  // Generic timer
-	setFeature(c, FCMA, "hw.optional.arm.FEAT_FCMA", "hw.optional.armv8_3_compnum")     // Floating point complex number addition and multiplication
-	setFeature(c, FHM, "hw.optional.armv8_2_fhm", "hw.optional.arm.FEAT_FHM")           // FMLAL and FMLSL instructions
-	setFeature(c, FP, "hw.optional.floatingpoint")                                      // Single-precision and double-precision floating point
-	setFeature(c, FPHP, "hw.optional.arm.FEAT_FP16", "hw.optional.neon_fp16")           // Half-precision floating point
-	setFeature(c, GPA, "hw.optional.arm.FEAT_PAuth")                                    // Generic Pointer Authentication
-	setFeature(c, JSCVT, "hw.optional.arm.FEAT_JSCVT")                                  // Javascript-style double->int convert (FJCVTZS)
-	setFeature(c, LRCPC, "hw.optional.arm.FEAT_LRCPC")                                  // Weaker release consistency (LDAPR, etc)
-	setFeature(c, PMULL, "hw.optional.arm.FEAT_PMULL")                                  // Polynomial Multiply instructions (PMULL/PMULL2)
-	setFeature(c, RNDR, "hw.optional.arm.FEAT_RNG")                                     // Random Number instructions
-	setFeature(c, TLB, "hw.optional.arm.FEAT_TLBIOS", "hw.optional.arm.FEAT_TLBIRANGE") // Outer Shareable and TLB range maintenance instructions
-	setFeature(c, TS, "hw.optional.arm.FEAT_FlagM", "hw.optional.arm.FEAT_FlagM2")      // Flag manipulation instructions
-	setFeature(c, SHA1, "hw.optional.arm.FEAT_SHA1")                                    // SHA-1 instructions (SHA1C, etc)
-	setFeature(c, SHA2, "hw.optional.arm.FEAT_SHA256")                                  // SHA-2 instructions (SHA256H, etc)
-	setFeature(c, SHA3, "hw.optional.arm.FEAT_SHA3")                                    // SHA-3 instructions (EOR3, RAXI, XAR, BCAX)
-	setFeature(c, SHA512, "hw.optional.arm.FEAT_SHA512")                                // SHA512 instructions
-	setFeature(c, SM3, "hw.optional.arm.FEAT_SM3")                                      // SM3 instructions
-	setFeature(c, SM4, "hw.optional.arm.FEAT_SM4")                                      // SM4 instructions
-	setFeature(c, SVE, "hw.optional.arm.FEAT_SVE")                                      // Scalable Vector Extension
+	// from https://developer.arm.com/downloads/-/exploration-tools/feature-names-for-a-profile
+	setFeature(c, "hw.optional.arm.FEAT_AES", AESARM)
+	setFeature(c, "hw.optional.AdvSIMD", ASIMD)
+	setFeature(c, "hw.optional.arm.FEAT_DotProd", ASIMDDP)
+	setFeature(c, "hw.optional.arm.FEAT_RDM", ASIMDRDM)
+	setFeature(c, "hw.optional.FEAT_CRC32", CRC32)
+	setFeature(c, "hw.optional.arm.FEAT_DPB", DCPOP)
+	// setFeature(c, "", EVTSTRM)
+	setFeature(c, "hw.optional.arm.FEAT_FCMA", FCMA)
+	setFeature(c, "hw.optional.arm.FEAT_FP", FP)
+	setFeature(c, "hw.optional.arm.FEAT_FP16", FPHP)
+	setFeature(c, "hw.optional.arm.FEAT_PAuth", GPA)
+	setFeature(c, "hw.optional.arm.FEAT_JSCVT", JSCVT)
+	setFeature(c, "hw.optional.arm.FEAT_LRCPC", LRCPC)
+	setFeature(c, "hw.optional.arm.FEAT_PMULL", PMULL)
+	setFeature(c, "hw.optional.arm.FEAT_SHA1", SHA1)
+	setFeature(c, "hw.optional.arm.FEAT_SHA256", SHA2)
+	setFeature(c, "hw.optional.arm.FEAT_SHA3", SHA3)
+	setFeature(c, "hw.optional.arm.FEAT_SHA512", SHA512)
+	// setFeature(c, "", SM3)
+	// setFeature(c, "", SM4)
+	setFeature(c, "hw.optional.arm.FEAT_SVE", SVE)
+
+	// from empirical observation
+	setFeature(c, "hw.optional.AdvSIMD_HPFPCvt", ASIMDHP)
+	setFeature(c, "hw.optional.armv8_1_atomics", ATOMICS)
+	setFeature(c, "hw.optional.floatingpoint", FP)
+	setFeature(c, "hw.optional.armv8_2_sha3", SHA3)
+	setFeature(c, "hw.optional.armv8_2_sha512", SHA512)
+	setFeature(c, "hw.optional.armv8_3_compnum", FCMA)
+	setFeature(c, "hw.optional.armv8_crc32", CRC32)
 }
--- a/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
+++ b/vendor/github.com/klauspost/cpuid/v2/os_linux_arm64.go
@@ -39,80 +39,6 @@ const (
 	hwcap_SHA512   = 1 << 21
 	hwcap_SVE      = 1 << 22
 	hwcap_ASIMDFHM = 1 << 23
-	hwcap_DIT      = 1 << 24
-	hwcap_USCAT    = 1 << 25
-	hwcap_ILRCPC   = 1 << 26
-	hwcap_FLAGM    = 1 << 27
-	hwcap_SSBS     = 1 << 28
-	hwcap_SB       = 1 << 29
-	hwcap_PACA     = 1 << 30
-	hwcap_PACG     = 1 << 31
-	hwcap_GCS      = 1 << 32
-
-	hwcap2_DCPODP      = 1 << 0
-	hwcap2_SVE2        = 1 << 1
-	hwcap2_SVEAES      = 1 << 2
-	hwcap2_SVEPMULL    = 1 << 3
-	hwcap2_SVEBITPERM  = 1 << 4
-	hwcap2_SVESHA3     = 1 << 5
-	hwcap2_SVESM4      = 1 << 6
-	hwcap2_FLAGM2      = 1 << 7
-	hwcap2_FRINT       = 1 << 8
-	hwcap2_SVEI8MM     = 1 << 9
-	hwcap2_SVEF32MM    = 1 << 10
-	hwcap2_SVEF64MM    = 1 << 11
-	hwcap2_SVEBF16     = 1 << 12
-	hwcap2_I8MM        = 1 << 13
-	hwcap2_BF16        = 1 << 14
-	hwcap2_DGH         = 1 << 15
-	hwcap2_RNG         = 1 << 16
-	hwcap2_BTI         = 1 << 17
-	hwcap2_MTE         = 1 << 18
-	hwcap2_ECV         = 1 << 19
-	hwcap2_AFP         = 1 << 20
-	hwcap2_RPRES       = 1 << 21
-	hwcap2_MTE3        = 1 << 22
-	hwcap2_SME         = 1 << 23
-	hwcap2_SME_I16I64  = 1 << 24
-	hwcap2_SME_F64F64  = 1 << 25
-	hwcap2_SME_I8I32   = 1 << 26
-	hwcap2_SME_F16F32  = 1 << 27
-	hwcap2_SME_B16F32  = 1 << 28
-	hwcap2_SME_F32F32  = 1 << 29
-	hwcap2_SME_FA64    = 1 << 30
-	hwcap2_WFXT        = 1 << 31
-	hwcap2_EBF16       = 1 << 32
-	hwcap2_SVE_EBF16   = 1 << 33
-	hwcap2_CSSC        = 1 << 34
-	hwcap2_RPRFM       = 1 << 35
-	hwcap2_SVE2P1      = 1 << 36
-	hwcap2_SME2        = 1 << 37
-	hwcap2_SME2P1      = 1 << 38
-	hwcap2_SME_I16I32  = 1 << 39
-	hwcap2_SME_BI32I32 = 1 << 40
-	hwcap2_SME_B16B16  = 1 << 41
-	hwcap2_SME_F16F16  = 1 << 42
-	hwcap2_MOPS        = 1 << 43
-	hwcap2_HBC         = 1 << 44
-	hwcap2_SVE_B16B16  = 1 << 45
-	hwcap2_LRCPC3      = 1 << 46
-	hwcap2_LSE128      = 1 << 47
-	hwcap2_FPMR        = 1 << 48
-	hwcap2_LUT         = 1 << 49
-	hwcap2_FAMINMAX    = 1 << 50
-	hwcap2_F8CVT       = 1 << 51
-	hwcap2_F8FMA       = 1 << 52
-	hwcap2_F8DP4       = 1 << 53
-	hwcap2_F8DP2       = 1 << 54
-	hwcap2_F8E4M3      = 1 << 55
-	hwcap2_F8E5M2      = 1 << 56
-	hwcap2_SME_LUTV2   = 1 << 57
-	hwcap2_SME_F8F16   = 1 << 58
-	hwcap2_SME_F8F32   = 1 << 59
-	hwcap2_SME_SF8FMA  = 1 << 60
-	hwcap2_SME_SF8DP4  = 1 << 61
-	hwcap2_SME_SF8DP2  = 1 << 62
-	hwcap2_POE         = 1 << 63
 )

 func detectOS(c *CPUInfo) bool {
@@ -178,15 +104,11 @@ func detectOS(c *CPUInfo) bool {
 	c.featureSet.setIf(isSet(hwcap, hwcap_DCPOP), DCPOP)
 	c.featureSet.setIf(isSet(hwcap, hwcap_EVTSTRM), EVTSTRM)
 	c.featureSet.setIf(isSet(hwcap, hwcap_FCMA), FCMA)
-	c.featureSet.setIf(isSet(hwcap, hwcap_ASIMDFHM), FHM)
 	c.featureSet.setIf(isSet(hwcap, hwcap_FP), FP)
 	c.featureSet.setIf(isSet(hwcap, hwcap_FPHP), FPHP)
 	c.featureSet.setIf(isSet(hwcap, hwcap_JSCVT), JSCVT)
 	c.featureSet.setIf(isSet(hwcap, hwcap_LRCPC), LRCPC)
 	c.featureSet.setIf(isSet(hwcap, hwcap_PMULL), PMULL)
-	c.featureSet.setIf(isSet(hwcap, hwcap2_RNG), RNDR)
-	// c.featureSet.setIf(isSet(hwcap, hwcap_), TLB)
-	// c.featureSet.setIf(isSet(hwcap, hwcap_), TS)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SHA1), SHA1)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SHA2), SHA2)
 	c.featureSet.setIf(isSet(hwcap, hwcap_SHA3), SHA3)