增加websocket支持
This commit is contained in:
475
vendor/github.com/klauspost/cpuid/v2/cpuid.go
generated
vendored
475
vendor/github.com/klauspost/cpuid/v2/cpuid.go
generated
vendored
@@ -67,200 +67,187 @@ const (
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// Keep index -1 as unknown
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UNKNOWN = -1
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// x86 features
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ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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AESNI // Advanced Encryption Standard New Instructions
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AMD3DNOW // AMD 3DNOW
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AMD3DNOWEXT // AMD 3DNowExt
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AMXBF16 // Tile computational operations on BFLOAT16 numbers
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AMXFP16 // Tile computational operations on FP16 numbers
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AMXINT8 // Tile computational operations on 8-bit integers
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AMXTILE // Tile architecture
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APX_F // Intel APX
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AVX // AVX functions
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AVX10 // If set the Intel AVX10 Converged Vector ISA is supported
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AVX10_128 // If set indicates that AVX10 128-bit vector support is present
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AVX10_256 // If set indicates that AVX10 256-bit vector support is present
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AVX10_512 // If set indicates that AVX10 512-bit vector support is present
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AVX2 // AVX2 functions
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AVX512BF16 // AVX-512 BFLOAT16 Instructions
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AVX512BITALG // AVX-512 Bit Algorithms
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AVX512BW // AVX-512 Byte and Word Instructions
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AVX512CD // AVX-512 Conflict Detection Instructions
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AVX512DQ // AVX-512 Doubleword and Quadword Instructions
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AVX512ER // AVX-512 Exponential and Reciprocal Instructions
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AVX512F // AVX-512 Foundation
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AVX512FP16 // AVX-512 FP16 Instructions
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AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
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AVX512PF // AVX-512 Prefetch Instructions
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AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
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AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2
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AVX512VL // AVX-512 Vector Length Extensions
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AVX512VNNI // AVX-512 Vector Neural Network Instructions
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
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AVXIFMA // AVX-IFMA instructions
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AVXNECONVERT // AVX-NE-CONVERT instructions
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AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
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AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
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AVXVNNIINT8 // AVX-VNNI-INT8 instructions
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BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598
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BMI1 // Bit Manipulation Instruction Set 1
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BMI2 // Bit Manipulation Instruction Set 2
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CETIBT // Intel CET Indirect Branch Tracking
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CETSS // Intel CET Shadow Stack
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CLDEMOTE // Cache Line Demote
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CLMUL // Carry-less Multiplication
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CLZERO // CLZERO instruction supported
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CMOV // i686 CMOV
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CMPCCXADD // CMPCCXADD instructions
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CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB
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CMPXCHG8 // CMPXCHG8 instruction
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CPBOOST // Core Performance Boost
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CPPC // AMD: Collaborative Processor Performance Control
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CX16 // CMPXCHG16B Instruction
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EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ
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ENQCMD // Enqueue Command
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ERMS // Enhanced REP MOVSB/STOSB
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F16C // Half-precision floating-point conversion
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FLUSH_L1D // Flush L1D cache
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FMA3 // Intel FMA 3. Does not imply AVX.
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FMA4 // Bulldozer FMA4 functions
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FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
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FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
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FSRM // Fast Short Rep Mov
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FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9
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FXSROPT // FXSAVE/FXRSTOR optimizations
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GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.
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HLE // Hardware Lock Elision
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HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR
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HTT // Hyperthreading (enabled)
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HWA // Hardware assert supported. Indicates support for MSRC001_10
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HYBRID_CPU // This part has CPUs of more than one type.
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HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
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IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel)
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IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR
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IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
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IBPB_BRTYPE // Indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch type predictions from the CPU branch predictor
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IBRS // AMD: Indirect Branch Restricted Speculation
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IBRS_PREFERRED // AMD: IBRS is preferred over software solution
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IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection
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IBS // Instruction Based Sampling (AMD)
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IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
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IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
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IBSFFV // Instruction Based Sampling Feature (AMD)
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IBSOPCNT // Instruction Based Sampling Feature (AMD)
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IBSOPCNTEXT // Instruction Based Sampling Feature (AMD)
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IBSOPSAM // Instruction Based Sampling Feature (AMD)
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IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
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IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
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IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported
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IBS_OPDATA4 // AMD: IBS op data 4 MSR supported
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IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
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IBS_PREVENTHOST // Disallowing IBS use by the host supported
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IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
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IDPRED_CTRL // IPRED_DIS
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INT_WBINVD // WBINVD/WBNOINVD are interruptible.
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INVLPGB // NVLPGB and TLBSYNC instruction supported
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KEYLOCKER // Key locker
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KEYLOCKERW // Key locker wide
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LAHF // LAHF/SAHF in long mode
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LAM // If set, CPU supports Linear Address Masking
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LBRVIRT // LBR virtualization
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LZCNT // LZCNT instruction
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MCAOVERFLOW // MCA overflow recovery support.
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MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.
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MCOMMIT // MCOMMIT instruction supported
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MD_CLEAR // VERW clears CPU buffers
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MMX // standard MMX
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MMXEXT // SSE integer functions or AMD MMX ext
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MOVBE // MOVBE instruction (big-endian)
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MOVDIR64B // Move 64 Bytes as Direct Store
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MOVDIRI // Move Doubleword as Direct Store
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MOVSB_ZL // Fast Zero-Length MOVSB
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MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD
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MPX // Intel MPX (Memory Protection Extensions)
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MSRIRC // Instruction Retired Counter MSR available
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MSRLIST // Read/Write List of Model Specific Registers
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MSR_PAGEFLUSH // Page Flush MSR available
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NRIPS // Indicates support for NRIP save on VMEXIT
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NX // NX (No-Execute) bit
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OSXSAVE // XSAVE enabled by OS
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PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption
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POPCNT // POPCNT instruction
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PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
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PREFETCHI // PREFETCHIT0/1 instructions
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PSFD // Predictive Store Forward Disable
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RDPRU // RDPRU instruction supported
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RDRAND // RDRAND instruction is available
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RDSEED // RDSEED instruction is available
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RDTSCP // RDTSCP Instruction
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RRSBA_CTRL // Restricted RSB Alternate
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RTM // Restricted Transactional Memory
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RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
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SBPB // Indicates support for the Selective Branch Predictor Barrier
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SERIALIZE // Serialize Instruction Execution
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SEV // AMD Secure Encrypted Virtualization supported
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SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host
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SEV_ALTERNATIVE // AMD SEV Alternate Injection supported
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SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests
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SEV_ES // AMD SEV Encrypted State supported
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SEV_RESTRICTED // AMD SEV Restricted Injection supported
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SEV_SNP // AMD SEV Secure Nested Paging supported
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SGX // Software Guard Extensions
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SGXLC // Software Guard Extensions Launch Control
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SHA // Intel SHA Extensions
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SME // AMD Secure Memory Encryption supported
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SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
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SPEC_CTRL_SSBD // Speculative Store Bypass Disable
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SRBDS_CTRL // SRBDS mitigation MSR available
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SRSO_MSR_FIX // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO.
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SRSO_NO // Indicates the CPU is not subject to the SRSO vulnerability
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SRSO_USER_KERNEL_NO // Indicates the CPU is not subject to the SRSO vulnerability across user/kernel boundaries
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SSE // SSE functions
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SSE2 // P4 SSE functions
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SSE3 // Prescott SSE3 functions
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SSE4 // Penryn SSE4.1 functions
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SSE42 // Nehalem SSE4.2 functions
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SSE4A // AMD Barcelona microarchitecture SSE4a instructions
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SSSE3 // Conroe SSSE3 functions
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STIBP // Single Thread Indirect Branch Predictors
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STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On
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STOSB_SHORT // Fast short STOSB
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SUCCOR // Software uncorrectable error containment and recovery capability.
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SVM // AMD Secure Virtual Machine
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SVMDA // Indicates support for the SVM decode assists.
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SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control
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SVML // AMD SVM lock. Indicates support for SVM-Lock.
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SVMNP // AMD SVM nested paging
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SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter
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SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold
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SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions.
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SYSEE // SYSENTER and SYSEXIT instructions
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TBM // AMD Trailing Bit Manipulation
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TDX_GUEST // Intel Trust Domain Extensions Guest
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TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations
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TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
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TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
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TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
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TSXLDTRK // Intel TSX Suspend Load Address Tracking
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VAES // Vector AES. AVX(512) versions requires additional checks.
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VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits.
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VMPL // AMD VM Permission Levels supported
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VMSA_REGPROT // AMD VMSA Register Protection supported
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VMX // Virtual Machine Extensions
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VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions.
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VTE // AMD Virtual Transparent Encryption supported
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WAITPKG // TPAUSE, UMONITOR, UMWAIT
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WBNOINVD // Write Back and Do Not Invalidate Cache
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WRMSRNS // Non-Serializing Write to Model Specific Register
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X87 // FPU
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XGETBV1 // Supports XGETBV with ECX = 1
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XOP // Bulldozer XOP functions
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XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV
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XSAVEC // Supports XSAVEC and the compacted form of XRSTOR.
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XSAVEOPT // XSAVEOPT available
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XSAVES // Supports XSAVES/XRSTORS and IA32_XSS
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// Add features
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ADX FeatureID = iota // Intel ADX (Multi-Precision Add-Carry Instruction Extensions)
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AESNI // Advanced Encryption Standard New Instructions
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AMD3DNOW // AMD 3DNOW
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AMD3DNOWEXT // AMD 3DNowExt
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AMXBF16 // Tile computational operations on BFLOAT16 numbers
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AMXFP16 // Tile computational operations on FP16 numbers
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AMXINT8 // Tile computational operations on 8-bit integers
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AMXTILE // Tile architecture
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AVX // AVX functions
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AVX2 // AVX2 functions
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AVX512BF16 // AVX-512 BFLOAT16 Instructions
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AVX512BITALG // AVX-512 Bit Algorithms
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AVX512BW // AVX-512 Byte and Word Instructions
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AVX512CD // AVX-512 Conflict Detection Instructions
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AVX512DQ // AVX-512 Doubleword and Quadword Instructions
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AVX512ER // AVX-512 Exponential and Reciprocal Instructions
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AVX512F // AVX-512 Foundation
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AVX512FP16 // AVX-512 FP16 Instructions
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AVX512IFMA // AVX-512 Integer Fused Multiply-Add Instructions
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AVX512PF // AVX-512 Prefetch Instructions
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AVX512VBMI // AVX-512 Vector Bit Manipulation Instructions
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AVX512VBMI2 // AVX-512 Vector Bit Manipulation Instructions, Version 2
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AVX512VL // AVX-512 Vector Length Extensions
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AVX512VNNI // AVX-512 Vector Neural Network Instructions
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AVX512VP2INTERSECT // AVX-512 Intersect for D/Q
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AVX512VPOPCNTDQ // AVX-512 Vector Population Count Doubleword and Quadword
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AVXIFMA // AVX-IFMA instructions
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AVXNECONVERT // AVX-NE-CONVERT instructions
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AVXSLOW // Indicates the CPU performs 2 128 bit operations instead of one
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AVXVNNI // AVX (VEX encoded) VNNI neural network instructions
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AVXVNNIINT8 // AVX-VNNI-INT8 instructions
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BHI_CTRL // Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598
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BMI1 // Bit Manipulation Instruction Set 1
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BMI2 // Bit Manipulation Instruction Set 2
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CETIBT // Intel CET Indirect Branch Tracking
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CETSS // Intel CET Shadow Stack
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||||
CLDEMOTE // Cache Line Demote
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||||
CLMUL // Carry-less Multiplication
|
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CLZERO // CLZERO instruction supported
|
||||
CMOV // i686 CMOV
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||||
CMPCCXADD // CMPCCXADD instructions
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||||
CMPSB_SCADBS_SHORT // Fast short CMPSB and SCASB
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||||
CMPXCHG8 // CMPXCHG8 instruction
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CPBOOST // Core Performance Boost
|
||||
CPPC // AMD: Collaborative Processor Performance Control
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||||
CX16 // CMPXCHG16B Instruction
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EFER_LMSLE_UNS // AMD: =Core::X86::Msr::EFER[LMSLE] is not supported, and MBZ
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||||
ENQCMD // Enqueue Command
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||||
ERMS // Enhanced REP MOVSB/STOSB
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||||
F16C // Half-precision floating-point conversion
|
||||
FLUSH_L1D // Flush L1D cache
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||||
FMA3 // Intel FMA 3. Does not imply AVX.
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||||
FMA4 // Bulldozer FMA4 functions
|
||||
FP128 // AMD: When set, the internal FP/SIMD execution datapath is no more than 128-bits wide
|
||||
FP256 // AMD: When set, the internal FP/SIMD execution datapath is no more than 256-bits wide
|
||||
FSRM // Fast Short Rep Mov
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||||
FXSR // FXSAVE, FXRESTOR instructions, CR4 bit 9
|
||||
FXSROPT // FXSAVE/FXRSTOR optimizations
|
||||
GFNI // Galois Field New Instructions. May require other features (AVX, AVX512VL,AVX512F) based on usage.
|
||||
HLE // Hardware Lock Elision
|
||||
HRESET // If set CPU supports history reset and the IA32_HRESET_ENABLE MSR
|
||||
HTT // Hyperthreading (enabled)
|
||||
HWA // Hardware assert supported. Indicates support for MSRC001_10
|
||||
HYBRID_CPU // This part has CPUs of more than one type.
|
||||
HYPERVISOR // This bit has been reserved by Intel & AMD for use by hypervisors
|
||||
IA32_ARCH_CAP // IA32_ARCH_CAPABILITIES MSR (Intel)
|
||||
IA32_CORE_CAP // IA32_CORE_CAPABILITIES MSR
|
||||
IBPB // Indirect Branch Restricted Speculation (IBRS) and Indirect Branch Predictor Barrier (IBPB)
|
||||
IBRS // AMD: Indirect Branch Restricted Speculation
|
||||
IBRS_PREFERRED // AMD: IBRS is preferred over software solution
|
||||
IBRS_PROVIDES_SMP // AMD: IBRS provides Same Mode Protection
|
||||
IBS // Instruction Based Sampling (AMD)
|
||||
IBSBRNTRGT // Instruction Based Sampling Feature (AMD)
|
||||
IBSFETCHSAM // Instruction Based Sampling Feature (AMD)
|
||||
IBSFFV // Instruction Based Sampling Feature (AMD)
|
||||
IBSOPCNT // Instruction Based Sampling Feature (AMD)
|
||||
IBSOPCNTEXT // Instruction Based Sampling Feature (AMD)
|
||||
IBSOPSAM // Instruction Based Sampling Feature (AMD)
|
||||
IBSRDWROPCNT // Instruction Based Sampling Feature (AMD)
|
||||
IBSRIPINVALIDCHK // Instruction Based Sampling Feature (AMD)
|
||||
IBS_FETCH_CTLX // AMD: IBS fetch control extended MSR supported
|
||||
IBS_OPDATA4 // AMD: IBS op data 4 MSR supported
|
||||
IBS_OPFUSE // AMD: Indicates support for IbsOpFuse
|
||||
IBS_PREVENTHOST // Disallowing IBS use by the host supported
|
||||
IBS_ZEN4 // AMD: Fetch and Op IBS support IBS extensions added with Zen4
|
||||
IDPRED_CTRL // IPRED_DIS
|
||||
INT_WBINVD // WBINVD/WBNOINVD are interruptible.
|
||||
INVLPGB // NVLPGB and TLBSYNC instruction supported
|
||||
LAHF // LAHF/SAHF in long mode
|
||||
LAM // If set, CPU supports Linear Address Masking
|
||||
LBRVIRT // LBR virtualization
|
||||
LZCNT // LZCNT instruction
|
||||
MCAOVERFLOW // MCA overflow recovery support.
|
||||
MCDT_NO // Processor do not exhibit MXCSR Configuration Dependent Timing behavior and do not need to mitigate it.
|
||||
MCOMMIT // MCOMMIT instruction supported
|
||||
MD_CLEAR // VERW clears CPU buffers
|
||||
MMX // standard MMX
|
||||
MMXEXT // SSE integer functions or AMD MMX ext
|
||||
MOVBE // MOVBE instruction (big-endian)
|
||||
MOVDIR64B // Move 64 Bytes as Direct Store
|
||||
MOVDIRI // Move Doubleword as Direct Store
|
||||
MOVSB_ZL // Fast Zero-Length MOVSB
|
||||
MOVU // AMD: MOVU SSE instructions are more efficient and should be preferred to SSE MOVL/MOVH. MOVUPS is more efficient than MOVLPS/MOVHPS. MOVUPD is more efficient than MOVLPD/MOVHPD
|
||||
MPX // Intel MPX (Memory Protection Extensions)
|
||||
MSRIRC // Instruction Retired Counter MSR available
|
||||
MSRLIST // Read/Write List of Model Specific Registers
|
||||
MSR_PAGEFLUSH // Page Flush MSR available
|
||||
NRIPS // Indicates support for NRIP save on VMEXIT
|
||||
NX // NX (No-Execute) bit
|
||||
OSXSAVE // XSAVE enabled by OS
|
||||
PCONFIG // PCONFIG for Intel Multi-Key Total Memory Encryption
|
||||
POPCNT // POPCNT instruction
|
||||
PPIN // AMD: Protected Processor Inventory Number support. Indicates that Protected Processor Inventory Number (PPIN) capability can be enabled
|
||||
PREFETCHI // PREFETCHIT0/1 instructions
|
||||
PSFD // Predictive Store Forward Disable
|
||||
RDPRU // RDPRU instruction supported
|
||||
RDRAND // RDRAND instruction is available
|
||||
RDSEED // RDSEED instruction is available
|
||||
RDTSCP // RDTSCP Instruction
|
||||
RRSBA_CTRL // Restricted RSB Alternate
|
||||
RTM // Restricted Transactional Memory
|
||||
RTM_ALWAYS_ABORT // Indicates that the loaded microcode is forcing RTM abort.
|
||||
SERIALIZE // Serialize Instruction Execution
|
||||
SEV // AMD Secure Encrypted Virtualization supported
|
||||
SEV_64BIT // AMD SEV guest execution only allowed from a 64-bit host
|
||||
SEV_ALTERNATIVE // AMD SEV Alternate Injection supported
|
||||
SEV_DEBUGSWAP // Full debug state swap supported for SEV-ES guests
|
||||
SEV_ES // AMD SEV Encrypted State supported
|
||||
SEV_RESTRICTED // AMD SEV Restricted Injection supported
|
||||
SEV_SNP // AMD SEV Secure Nested Paging supported
|
||||
SGX // Software Guard Extensions
|
||||
SGXLC // Software Guard Extensions Launch Control
|
||||
SHA // Intel SHA Extensions
|
||||
SME // AMD Secure Memory Encryption supported
|
||||
SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
|
||||
SPEC_CTRL_SSBD // Speculative Store Bypass Disable
|
||||
SRBDS_CTRL // SRBDS mitigation MSR available
|
||||
SSE // SSE functions
|
||||
SSE2 // P4 SSE functions
|
||||
SSE3 // Prescott SSE3 functions
|
||||
SSE4 // Penryn SSE4.1 functions
|
||||
SSE42 // Nehalem SSE4.2 functions
|
||||
SSE4A // AMD Barcelona microarchitecture SSE4a instructions
|
||||
SSSE3 // Conroe SSSE3 functions
|
||||
STIBP // Single Thread Indirect Branch Predictors
|
||||
STIBP_ALWAYSON // AMD: Single Thread Indirect Branch Prediction Mode has Enhanced Performance and may be left Always On
|
||||
STOSB_SHORT // Fast short STOSB
|
||||
SUCCOR // Software uncorrectable error containment and recovery capability.
|
||||
SVM // AMD Secure Virtual Machine
|
||||
SVMDA // Indicates support for the SVM decode assists.
|
||||
SVMFBASID // SVM, Indicates that TLB flush events, including CR3 writes and CR4.PGE toggles, flush only the current ASID's TLB entries. Also indicates support for the extended VMCBTLB_Control
|
||||
SVML // AMD SVM lock. Indicates support for SVM-Lock.
|
||||
SVMNP // AMD SVM nested paging
|
||||
SVMPF // SVM pause intercept filter. Indicates support for the pause intercept filter
|
||||
SVMPFT // SVM PAUSE filter threshold. Indicates support for the PAUSE filter cycle count threshold
|
||||
SYSCALL // System-Call Extension (SCE): SYSCALL and SYSRET instructions.
|
||||
SYSEE // SYSENTER and SYSEXIT instructions
|
||||
TBM // AMD Trailing Bit Manipulation
|
||||
TLB_FLUSH_NESTED // AMD: Flushing includes all the nested translations for guest translations
|
||||
TME // Intel Total Memory Encryption. The following MSRs are supported: IA32_TME_CAPABILITY, IA32_TME_ACTIVATE, IA32_TME_EXCLUDE_MASK, and IA32_TME_EXCLUDE_BASE.
|
||||
TOPEXT // TopologyExtensions: topology extensions support. Indicates support for CPUID Fn8000_001D_EAX_x[N:0]-CPUID Fn8000_001E_EDX.
|
||||
TSCRATEMSR // MSR based TSC rate control. Indicates support for MSR TSC ratio MSRC000_0104
|
||||
TSXLDTRK // Intel TSX Suspend Load Address Tracking
|
||||
VAES // Vector AES. AVX(512) versions requires additional checks.
|
||||
VMCBCLEAN // VMCB clean bits. Indicates support for VMCB clean bits.
|
||||
VMPL // AMD VM Permission Levels supported
|
||||
VMSA_REGPROT // AMD VMSA Register Protection supported
|
||||
VMX // Virtual Machine Extensions
|
||||
VPCLMULQDQ // Carry-Less Multiplication Quadword. Requires AVX for 3 register versions.
|
||||
VTE // AMD Virtual Transparent Encryption supported
|
||||
WAITPKG // TPAUSE, UMONITOR, UMWAIT
|
||||
WBNOINVD // Write Back and Do Not Invalidate Cache
|
||||
WRMSRNS // Non-Serializing Write to Model Specific Register
|
||||
X87 // FPU
|
||||
XGETBV1 // Supports XGETBV with ECX = 1
|
||||
XOP // Bulldozer XOP functions
|
||||
XSAVE // XSAVE, XRESTOR, XSETBV, XGETBV
|
||||
XSAVEC // Supports XSAVEC and the compacted form of XRSTOR.
|
||||
XSAVEOPT // XSAVEOPT available
|
||||
XSAVES // Supports XSAVES/XRSTORS and IA32_XSS
|
||||
|
||||
// ARM features:
|
||||
AESARM // AES instructions
|
||||
@@ -314,11 +301,9 @@ type CPUInfo struct {
|
||||
L2 int // L2 Cache (per core or shared). Will be -1 if undetected
|
||||
L3 int // L3 Cache (per core, per ccx or shared). Will be -1 if undetected
|
||||
}
|
||||
SGX SGXSupport
|
||||
AMDMemEncryption AMDMemEncryptionSupport
|
||||
AVX10Level uint8
|
||||
maxFunc uint32
|
||||
maxExFunc uint32
|
||||
SGX SGXSupport
|
||||
maxFunc uint32
|
||||
maxExFunc uint32
|
||||
}
|
||||
|
||||
var cpuid func(op uint32) (eax, ebx, ecx, edx uint32)
|
||||
@@ -1085,32 +1070,6 @@ func hasSGX(available, lc bool) (rval SGXSupport) {
|
||||
return
|
||||
}
|
||||
|
||||
type AMDMemEncryptionSupport struct {
|
||||
Available bool
|
||||
CBitPossition uint32
|
||||
NumVMPL uint32
|
||||
PhysAddrReduction uint32
|
||||
NumEntryptedGuests uint32
|
||||
MinSevNoEsAsid uint32
|
||||
}
|
||||
|
||||
func hasAMDMemEncryption(available bool) (rval AMDMemEncryptionSupport) {
|
||||
rval.Available = available
|
||||
if !available {
|
||||
return
|
||||
}
|
||||
|
||||
_, b, c, d := cpuidex(0x8000001f, 0)
|
||||
|
||||
rval.CBitPossition = b & 0x3f
|
||||
rval.PhysAddrReduction = (b >> 6) & 0x3F
|
||||
rval.NumVMPL = (b >> 12) & 0xf
|
||||
rval.NumEntryptedGuests = c
|
||||
rval.MinSevNoEsAsid = d
|
||||
|
||||
return
|
||||
}
|
||||
|
||||
func support() flagSet {
|
||||
var fs flagSet
|
||||
mfi := maxFunctionID()
|
||||
@@ -1205,7 +1164,6 @@ func support() flagSet {
|
||||
fs.setIf(ecx&(1<<10) != 0, VPCLMULQDQ)
|
||||
fs.setIf(ecx&(1<<13) != 0, TME)
|
||||
fs.setIf(ecx&(1<<25) != 0, CLDEMOTE)
|
||||
fs.setIf(ecx&(1<<23) != 0, KEYLOCKER)
|
||||
fs.setIf(ecx&(1<<27) != 0, MOVDIRI)
|
||||
fs.setIf(ecx&(1<<28) != 0, MOVDIR64B)
|
||||
fs.setIf(ecx&(1<<29) != 0, ENQCMD)
|
||||
@@ -1228,8 +1186,13 @@ func support() flagSet {
|
||||
fs.setIf(edx&(1<<30) != 0, IA32_CORE_CAP)
|
||||
fs.setIf(edx&(1<<31) != 0, SPEC_CTRL_SSBD)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EDX
|
||||
fs.setIf(edx&(1<<4) != 0, AVXVNNIINT8)
|
||||
fs.setIf(edx&(1<<5) != 0, AVXNECONVERT)
|
||||
fs.setIf(edx&(1<<14) != 0, PREFETCHI)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EAX
|
||||
eax1, _, _, edx1 := cpuidex(7, 1)
|
||||
eax1, _, _, _ := cpuidex(7, 1)
|
||||
fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI)
|
||||
fs.setIf(eax1&(1<<7) != 0, CMPCCXADD)
|
||||
fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
|
||||
@@ -1239,13 +1202,6 @@ func support() flagSet {
|
||||
fs.setIf(eax1&(1<<23) != 0, AVXIFMA)
|
||||
fs.setIf(eax1&(1<<26) != 0, LAM)
|
||||
|
||||
// CPUID.(EAX=7, ECX=1).EDX
|
||||
fs.setIf(edx1&(1<<4) != 0, AVXVNNIINT8)
|
||||
fs.setIf(edx1&(1<<5) != 0, AVXNECONVERT)
|
||||
fs.setIf(edx1&(1<<14) != 0, PREFETCHI)
|
||||
fs.setIf(edx1&(1<<19) != 0, AVX10)
|
||||
fs.setIf(edx1&(1<<21) != 0, APX_F)
|
||||
|
||||
// Only detect AVX-512 features if XGETBV is supported
|
||||
if c&((1<<26)|(1<<27)) == (1<<26)|(1<<27) {
|
||||
// Check for OS support
|
||||
@@ -1295,19 +1251,6 @@ func support() flagSet {
|
||||
fs.setIf(edx&(1<<4) != 0, BHI_CTRL)
|
||||
fs.setIf(edx&(1<<5) != 0, MCDT_NO)
|
||||
|
||||
// Add keylocker features.
|
||||
if fs.inSet(KEYLOCKER) && mfi >= 0x19 {
|
||||
_, ebx, _, _ := cpuidex(0x19, 0)
|
||||
fs.setIf(ebx&5 == 5, KEYLOCKERW) // Bit 0 and 2 (1+4)
|
||||
}
|
||||
|
||||
// Add AVX10 features.
|
||||
if fs.inSet(AVX10) && mfi >= 0x24 {
|
||||
_, ebx, _, _ := cpuidex(0x24, 0)
|
||||
fs.setIf(ebx&(1<<16) != 0, AVX10_128)
|
||||
fs.setIf(ebx&(1<<17) != 0, AVX10_256)
|
||||
fs.setIf(ebx&(1<<18) != 0, AVX10_512)
|
||||
}
|
||||
}
|
||||
|
||||
// Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
|
||||
@@ -1450,47 +1393,9 @@ func support() flagSet {
|
||||
fs.setIf((a>>24)&1 == 1, VMSA_REGPROT)
|
||||
}
|
||||
|
||||
if maxExtendedFunction() >= 0x80000021 && vend == AMD {
|
||||
a, _, _, _ := cpuid(0x80000021)
|
||||
fs.setIf((a>>31)&1 == 1, SRSO_MSR_FIX)
|
||||
fs.setIf((a>>30)&1 == 1, SRSO_USER_KERNEL_NO)
|
||||
fs.setIf((a>>29)&1 == 1, SRSO_NO)
|
||||
fs.setIf((a>>28)&1 == 1, IBPB_BRTYPE)
|
||||
fs.setIf((a>>27)&1 == 1, SBPB)
|
||||
}
|
||||
|
||||
if mfi >= 0x20 {
|
||||
// Microsoft has decided to purposefully hide the information
|
||||
// of the guest TEE when VMs are being created using Hyper-V.
|
||||
//
|
||||
// This leads us to check for the Hyper-V cpuid features
|
||||
// (0x4000000C), and then for the `ebx` value set.
|
||||
//
|
||||
// For Intel TDX, `ebx` is set as `0xbe3`, being 3 the part
|
||||
// we're mostly interested about,according to:
|
||||
// https://github.com/torvalds/linux/blob/d2f51b3516dade79269ff45eae2a7668ae711b25/arch/x86/include/asm/hyperv-tlfs.h#L169-L174
|
||||
_, ebx, _, _ := cpuid(0x4000000C)
|
||||
fs.setIf(ebx == 0xbe3, TDX_GUEST)
|
||||
}
|
||||
|
||||
if mfi >= 0x21 {
|
||||
// Intel Trusted Domain Extensions Guests have their own cpuid leaf (0x21).
|
||||
_, ebx, ecx, edx := cpuid(0x21)
|
||||
identity := string(valAsString(ebx, edx, ecx))
|
||||
fs.setIf(identity == "IntelTDX ", TDX_GUEST)
|
||||
}
|
||||
|
||||
return fs
|
||||
}
|
||||
|
||||
func (c *CPUInfo) supportAVX10() uint8 {
|
||||
if c.maxFunc >= 0x24 && c.featureSet.inSet(AVX10) {
|
||||
_, ebx, _, _ := cpuidex(0x24, 0)
|
||||
return uint8(ebx)
|
||||
}
|
||||
return 0
|
||||
}
|
||||
|
||||
func valAsString(values ...uint32) []byte {
|
||||
r := make([]byte, 4*len(values))
|
||||
for i, v := range values {
|
||||
|
||||
Reference in New Issue
Block a user