1033 lines
13 KiB
Go
1033 lines
13 KiB
Go
// cmd/9c/9.out.h from Vita Nuova.
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//
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// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved.
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// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
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// Portions Copyright © 1997-1999 Vita Nuova Limited
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// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
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// Portions Copyright © 2004,2006 Bruce Ellis
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// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
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// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
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// Portions Copyright © 2009 The Go Authors. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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// THE SOFTWARE.
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package ppc64
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import "github.com/twitchyliquid64/golang-asm/obj"
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//go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
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/*
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* powerpc 64
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*/
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const (
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NSNAME = 8
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NSYM = 50
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NREG = 32 /* number of general registers */
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NFREG = 32 /* number of floating point registers */
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)
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const (
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/* RBasePPC64 = 4096 */
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/* R0=4096 ... R31=4127 */
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REG_R0 = obj.RBasePPC64 + iota
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REG_R1
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REG_R2
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REG_R3
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REG_R4
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REG_R5
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REG_R6
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REG_R7
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REG_R8
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REG_R9
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REG_R10
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REG_R11
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REG_R12
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REG_R13
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REG_R14
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REG_R15
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REG_R16
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REG_R17
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REG_R18
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REG_R19
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REG_R20
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REG_R21
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REG_R22
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REG_R23
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REG_R24
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REG_R25
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REG_R26
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REG_R27
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REG_R28
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REG_R29
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REG_R30
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REG_R31
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/* F0=4128 ... F31=4159 */
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REG_F0
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REG_F1
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REG_F2
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REG_F3
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REG_F4
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REG_F5
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REG_F6
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REG_F7
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REG_F8
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REG_F9
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REG_F10
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REG_F11
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REG_F12
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REG_F13
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REG_F14
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REG_F15
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REG_F16
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REG_F17
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REG_F18
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REG_F19
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REG_F20
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REG_F21
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REG_F22
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REG_F23
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REG_F24
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REG_F25
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REG_F26
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REG_F27
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REG_F28
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REG_F29
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REG_F30
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REG_F31
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/* V0=4160 ... V31=4191 */
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REG_V0
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REG_V1
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REG_V2
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REG_V3
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REG_V4
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REG_V5
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REG_V6
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REG_V7
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REG_V8
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REG_V9
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REG_V10
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REG_V11
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REG_V12
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REG_V13
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REG_V14
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REG_V15
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REG_V16
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REG_V17
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REG_V18
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REG_V19
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REG_V20
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REG_V21
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REG_V22
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REG_V23
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REG_V24
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REG_V25
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REG_V26
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REG_V27
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REG_V28
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REG_V29
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REG_V30
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REG_V31
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/* VS0=4192 ... VS63=4255 */
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REG_VS0
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REG_VS1
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REG_VS2
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REG_VS3
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REG_VS4
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REG_VS5
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REG_VS6
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REG_VS7
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REG_VS8
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REG_VS9
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REG_VS10
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REG_VS11
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REG_VS12
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REG_VS13
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REG_VS14
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REG_VS15
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REG_VS16
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REG_VS17
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REG_VS18
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REG_VS19
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REG_VS20
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REG_VS21
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REG_VS22
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REG_VS23
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REG_VS24
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REG_VS25
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REG_VS26
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REG_VS27
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REG_VS28
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REG_VS29
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REG_VS30
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REG_VS31
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REG_VS32
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REG_VS33
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REG_VS34
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REG_VS35
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REG_VS36
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REG_VS37
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REG_VS38
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REG_VS39
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REG_VS40
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REG_VS41
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REG_VS42
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REG_VS43
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REG_VS44
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REG_VS45
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REG_VS46
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REG_VS47
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REG_VS48
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REG_VS49
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REG_VS50
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REG_VS51
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REG_VS52
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REG_VS53
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REG_VS54
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REG_VS55
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REG_VS56
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REG_VS57
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REG_VS58
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REG_VS59
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REG_VS60
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REG_VS61
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REG_VS62
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REG_VS63
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REG_CR0
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REG_CR1
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REG_CR2
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REG_CR3
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REG_CR4
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REG_CR5
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REG_CR6
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REG_CR7
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REG_MSR
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REG_FPSCR
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REG_CR
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REG_SPECIAL = REG_CR0
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REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
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REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers
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REG_XER = REG_SPR0 + 1
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REG_LR = REG_SPR0 + 8
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REG_CTR = REG_SPR0 + 9
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REGZERO = REG_R0 /* set to zero */
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REGSP = REG_R1
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REGSB = REG_R2
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REGRET = REG_R3
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REGARG = -1 /* -1 disables passing the first argument in register */
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REGRT1 = REG_R3 /* reserved for runtime, duffzero and duffcopy */
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REGRT2 = REG_R4 /* reserved for runtime, duffcopy */
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REGMIN = REG_R7 /* register variables allocated from here to REGMAX */
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REGCTXT = REG_R11 /* context for closures */
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REGTLS = REG_R13 /* C ABI TLS base pointer */
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REGMAX = REG_R27
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REGEXT = REG_R30 /* external registers allocated from here down */
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REGG = REG_R30 /* G */
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REGTMP = REG_R31 /* used by the linker */
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FREGRET = REG_F0
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FREGMIN = REG_F17 /* first register variable */
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FREGMAX = REG_F26 /* last register variable for 9g only */
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FREGEXT = REG_F26 /* first external register */
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)
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// OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI
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// https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
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var PPC64DWARFRegisters = map[int16]int16{}
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func init() {
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// f assigns dwarfregister[from:to] = (base):(to-from+base)
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f := func(from, to, base int16) {
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for r := int16(from); r <= to; r++ {
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PPC64DWARFRegisters[r] = r - from + base
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}
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}
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f(REG_R0, REG_R31, 0)
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f(REG_F0, REG_F31, 32)
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f(REG_V0, REG_V31, 77)
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f(REG_CR0, REG_CR7, 68)
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f(REG_VS0, REG_VS31, 32) // overlaps F0-F31
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f(REG_VS32, REG_VS63, 77) // overlaps V0-V31
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PPC64DWARFRegisters[REG_LR] = 65
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PPC64DWARFRegisters[REG_CTR] = 66
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PPC64DWARFRegisters[REG_XER] = 76
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}
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/*
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* GENERAL:
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*
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* compiler allocates R3 up as temps
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* compiler allocates register variables R7-R27
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* compiler allocates external registers R30 down
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*
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* compiler allocates register variables F17-F26
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* compiler allocates external registers F26 down
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*/
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const (
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BIG = 32768 - 8
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)
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const (
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/* mark flags */
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LABEL = 1 << 0
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LEAF = 1 << 1
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FLOAT = 1 << 2
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BRANCH = 1 << 3
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LOAD = 1 << 4
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FCMP = 1 << 5
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SYNC = 1 << 6
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LIST = 1 << 7
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FOLL = 1 << 8
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NOSCHED = 1 << 9
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)
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// Values for use in branch instruction BC
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// BC B0,BI,label
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// BO is type of branch + likely bits described below
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// BI is CR value + branch type
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// ex: BEQ CR2,label is BC 12,10,label
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// 12 = BO_BCR
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// 10 = BI_CR2 + BI_EQ
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const (
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BI_CR0 = 0
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BI_CR1 = 4
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BI_CR2 = 8
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BI_CR3 = 12
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BI_CR4 = 16
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BI_CR5 = 20
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BI_CR6 = 24
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BI_CR7 = 28
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BI_LT = 0
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BI_GT = 1
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BI_EQ = 2
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BI_OVF = 3
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)
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// Values for the BO field. Add the branch type to
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// the likely bits, if a likely setting is known.
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// If branch likely or unlikely is not known, don't set it.
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// e.g. branch on cr+likely = 15
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const (
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BO_BCTR = 16 // branch on ctr value
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BO_BCR = 12 // branch on cr value
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BO_BCRBCTR = 8 // branch on ctr and cr value
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BO_NOTBCR = 4 // branch on not cr value
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BO_UNLIKELY = 2 // value for unlikely
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BO_LIKELY = 3 // value for likely
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)
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// Bit settings from the CR
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const (
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C_COND_LT = iota // 0 result is negative
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C_COND_GT // 1 result is positive
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C_COND_EQ // 2 result is zero
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C_COND_SO // 3 summary overflow or FP compare w/ NaN
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)
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const (
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C_NONE = iota
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C_REG
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C_FREG
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C_VREG
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C_VSREG
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C_CREG
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C_SPR /* special processor register */
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C_ZCON
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C_SCON /* 16 bit signed */
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C_UCON /* 32 bit signed, low 16 bits 0 */
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C_ADDCON /* -0x8000 <= v < 0 */
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C_ANDCON /* 0 < v <= 0xFFFF */
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C_LCON /* other 32 */
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C_DCON /* other 64 (could subdivide further) */
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C_SACON /* $n(REG) where n <= int16 */
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C_SECON
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C_LACON /* $n(REG) where int16 < n <= int32 */
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C_LECON
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C_DACON /* $n(REG) where int32 < n */
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C_SBRA
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C_LBRA
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C_LBRAPIC
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C_SAUTO
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C_LAUTO
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C_SEXT
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C_LEXT
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C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG
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C_SOREG // register + signed offset
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C_LOREG
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C_FPSCR
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C_MSR
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C_XER
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C_LR
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C_CTR
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C_ANY
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C_GOK
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C_ADDR
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C_GOTADDR
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C_TOCADDR
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C_TLS_LE
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C_TLS_IE
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C_TEXTSIZE
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C_NCLASS /* must be the last */
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)
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const (
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AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
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AADDCC
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AADDIS
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AADDV
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AADDVCC
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AADDC
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AADDCCC
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AADDCV
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AADDCVCC
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AADDME
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AADDMECC
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AADDMEVCC
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AADDMEV
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AADDE
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AADDECC
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AADDEVCC
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AADDEV
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AADDZE
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AADDZECC
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AADDZEVCC
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AADDZEV
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AADDEX
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AAND
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AANDCC
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AANDN
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AANDNCC
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AANDISCC
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ABC
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ABCL
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ABEQ
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ABGE // not LT = G/E/U
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ABGT
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ABLE // not GT = L/E/U
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ABLT
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ABNE // not EQ = L/G/U
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ABVC // Unordered-clear
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ABVS // Unordered-set
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ACMP
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ACMPU
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ACMPEQB
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ACNTLZW
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ACNTLZWCC
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ACRAND
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ACRANDN
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ACREQV
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ACRNAND
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ACRNOR
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ACROR
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ACRORN
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ACRXOR
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ADIVW
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ADIVWCC
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ADIVWVCC
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ADIVWV
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ADIVWU
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ADIVWUCC
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ADIVWUVCC
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ADIVWUV
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AMODUD
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AMODUW
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AMODSD
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AMODSW
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AEQV
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AEQVCC
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AEXTSB
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AEXTSBCC
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AEXTSH
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AEXTSHCC
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AFABS
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AFABSCC
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AFADD
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AFADDCC
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AFADDS
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AFADDSCC
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AFCMPO
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AFCMPU
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AFCTIW
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AFCTIWCC
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AFCTIWZ
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AFCTIWZCC
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AFDIV
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AFDIVCC
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AFDIVS
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AFDIVSCC
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AFMADD
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AFMADDCC
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AFMADDS
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AFMADDSCC
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AFMOVD
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AFMOVDCC
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AFMOVDU
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AFMOVS
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AFMOVSU
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AFMOVSX
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AFMOVSZ
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AFMSUB
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AFMSUBCC
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AFMSUBS
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AFMSUBSCC
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AFMUL
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AFMULCC
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AFMULS
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AFMULSCC
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AFNABS
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AFNABSCC
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AFNEG
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AFNEGCC
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AFNMADD
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AFNMADDCC
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AFNMADDS
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AFNMADDSCC
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AFNMSUB
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AFNMSUBCC
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AFNMSUBS
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AFNMSUBSCC
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AFRSP
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AFRSPCC
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AFSUB
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AFSUBCC
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AFSUBS
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AFSUBSCC
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AISEL
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AMOVMW
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ALBAR
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ALHAR
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ALSW
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ALWAR
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ALWSYNC
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AMOVDBR
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AMOVWBR
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AMOVB
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AMOVBU
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AMOVBZ
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AMOVBZU
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AMOVH
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AMOVHBR
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AMOVHU
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AMOVHZ
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AMOVHZU
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AMOVW
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AMOVWU
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AMOVFL
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AMOVCRFS
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AMTFSB0
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AMTFSB0CC
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AMTFSB1
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AMTFSB1CC
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AMULHW
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AMULHWCC
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AMULHWU
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AMULHWUCC
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AMULLW
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AMULLWCC
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AMULLWVCC
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AMULLWV
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ANAND
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ANANDCC
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ANEG
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ANEGCC
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ANEGVCC
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ANEGV
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ANOR
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ANORCC
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AOR
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AORCC
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AORN
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AORNCC
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AORIS
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AREM
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AREMU
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ARFI
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ARLWMI
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ARLWMICC
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ARLWNM
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ARLWNMCC
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ACLRLSLWI
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ASLW
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ASLWCC
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ASRW
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ASRAW
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ASRAWCC
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ASRWCC
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ASTBCCC
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ASTHCCC
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ASTSW
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ASTWCCC
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ASUB
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ASUBCC
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ASUBVCC
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ASUBC
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ASUBCCC
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ASUBCV
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ASUBCVCC
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ASUBME
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ASUBMECC
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ASUBMEVCC
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ASUBMEV
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ASUBV
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ASUBE
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ASUBECC
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ASUBEV
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ASUBEVCC
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ASUBZE
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ASUBZECC
|
|
ASUBZEVCC
|
|
ASUBZEV
|
|
ASYNC
|
|
AXOR
|
|
AXORCC
|
|
AXORIS
|
|
|
|
ADCBF
|
|
ADCBI
|
|
ADCBST
|
|
ADCBT
|
|
ADCBTST
|
|
ADCBZ
|
|
AECIWX
|
|
AECOWX
|
|
AEIEIO
|
|
AICBI
|
|
AISYNC
|
|
APTESYNC
|
|
ATLBIE
|
|
ATLBIEL
|
|
ATLBSYNC
|
|
ATW
|
|
|
|
ASYSCALL
|
|
AWORD
|
|
|
|
ARFCI
|
|
|
|
AFCPSGN
|
|
AFCPSGNCC
|
|
/* optional on 32-bit */
|
|
AFRES
|
|
AFRESCC
|
|
AFRIM
|
|
AFRIMCC
|
|
AFRIP
|
|
AFRIPCC
|
|
AFRIZ
|
|
AFRIZCC
|
|
AFRIN
|
|
AFRINCC
|
|
AFRSQRTE
|
|
AFRSQRTECC
|
|
AFSEL
|
|
AFSELCC
|
|
AFSQRT
|
|
AFSQRTCC
|
|
AFSQRTS
|
|
AFSQRTSCC
|
|
|
|
/* 64-bit */
|
|
|
|
ACNTLZD
|
|
ACNTLZDCC
|
|
ACMPW /* CMP with L=0 */
|
|
ACMPWU
|
|
ACMPB
|
|
AFTDIV
|
|
AFTSQRT
|
|
ADIVD
|
|
ADIVDCC
|
|
ADIVDE
|
|
ADIVDECC
|
|
ADIVDEU
|
|
ADIVDEUCC
|
|
ADIVDVCC
|
|
ADIVDV
|
|
ADIVDU
|
|
ADIVDUCC
|
|
ADIVDUVCC
|
|
ADIVDUV
|
|
AEXTSW
|
|
AEXTSWCC
|
|
/* AFCFIW; AFCFIWCC */
|
|
AFCFID
|
|
AFCFIDCC
|
|
AFCFIDU
|
|
AFCFIDUCC
|
|
AFCFIDS
|
|
AFCFIDSCC
|
|
AFCTID
|
|
AFCTIDCC
|
|
AFCTIDZ
|
|
AFCTIDZCC
|
|
ALDAR
|
|
AMOVD
|
|
AMOVDU
|
|
AMOVWZ
|
|
AMOVWZU
|
|
AMULHD
|
|
AMULHDCC
|
|
AMULHDU
|
|
AMULHDUCC
|
|
AMULLD
|
|
AMULLDCC
|
|
AMULLDVCC
|
|
AMULLDV
|
|
ARFID
|
|
ARLDMI
|
|
ARLDMICC
|
|
ARLDIMI
|
|
ARLDIMICC
|
|
ARLDC
|
|
ARLDCCC
|
|
ARLDCR
|
|
ARLDCRCC
|
|
ARLDICR
|
|
ARLDICRCC
|
|
ARLDCL
|
|
ARLDCLCC
|
|
ARLDICL
|
|
ARLDICLCC
|
|
ARLDIC
|
|
ARLDICCC
|
|
ACLRLSLDI
|
|
AROTL
|
|
AROTLW
|
|
ASLBIA
|
|
ASLBIE
|
|
ASLBMFEE
|
|
ASLBMFEV
|
|
ASLBMTE
|
|
ASLD
|
|
ASLDCC
|
|
ASRD
|
|
ASRAD
|
|
ASRADCC
|
|
ASRDCC
|
|
ASTDCCC
|
|
ATD
|
|
|
|
/* 64-bit pseudo operation */
|
|
ADWORD
|
|
AREMD
|
|
AREMDU
|
|
|
|
/* more 64-bit operations */
|
|
AHRFID
|
|
APOPCNTD
|
|
APOPCNTW
|
|
APOPCNTB
|
|
ACNTTZW
|
|
ACNTTZWCC
|
|
ACNTTZD
|
|
ACNTTZDCC
|
|
ACOPY
|
|
APASTECC
|
|
ADARN
|
|
ALDMX
|
|
AMADDHD
|
|
AMADDHDU
|
|
AMADDLD
|
|
|
|
/* Vector */
|
|
ALV
|
|
ALVEBX
|
|
ALVEHX
|
|
ALVEWX
|
|
ALVX
|
|
ALVXL
|
|
ALVSL
|
|
ALVSR
|
|
ASTV
|
|
ASTVEBX
|
|
ASTVEHX
|
|
ASTVEWX
|
|
ASTVX
|
|
ASTVXL
|
|
AVAND
|
|
AVANDC
|
|
AVNAND
|
|
AVOR
|
|
AVORC
|
|
AVNOR
|
|
AVXOR
|
|
AVEQV
|
|
AVADDUM
|
|
AVADDUBM
|
|
AVADDUHM
|
|
AVADDUWM
|
|
AVADDUDM
|
|
AVADDUQM
|
|
AVADDCU
|
|
AVADDCUQ
|
|
AVADDCUW
|
|
AVADDUS
|
|
AVADDUBS
|
|
AVADDUHS
|
|
AVADDUWS
|
|
AVADDSS
|
|
AVADDSBS
|
|
AVADDSHS
|
|
AVADDSWS
|
|
AVADDE
|
|
AVADDEUQM
|
|
AVADDECUQ
|
|
AVSUBUM
|
|
AVSUBUBM
|
|
AVSUBUHM
|
|
AVSUBUWM
|
|
AVSUBUDM
|
|
AVSUBUQM
|
|
AVSUBCU
|
|
AVSUBCUQ
|
|
AVSUBCUW
|
|
AVSUBUS
|
|
AVSUBUBS
|
|
AVSUBUHS
|
|
AVSUBUWS
|
|
AVSUBSS
|
|
AVSUBSBS
|
|
AVSUBSHS
|
|
AVSUBSWS
|
|
AVSUBE
|
|
AVSUBEUQM
|
|
AVSUBECUQ
|
|
AVMULESB
|
|
AVMULOSB
|
|
AVMULEUB
|
|
AVMULOUB
|
|
AVMULESH
|
|
AVMULOSH
|
|
AVMULEUH
|
|
AVMULOUH
|
|
AVMULESW
|
|
AVMULOSW
|
|
AVMULEUW
|
|
AVMULOUW
|
|
AVMULUWM
|
|
AVPMSUM
|
|
AVPMSUMB
|
|
AVPMSUMH
|
|
AVPMSUMW
|
|
AVPMSUMD
|
|
AVMSUMUDM
|
|
AVR
|
|
AVRLB
|
|
AVRLH
|
|
AVRLW
|
|
AVRLD
|
|
AVS
|
|
AVSLB
|
|
AVSLH
|
|
AVSLW
|
|
AVSL
|
|
AVSLO
|
|
AVSRB
|
|
AVSRH
|
|
AVSRW
|
|
AVSR
|
|
AVSRO
|
|
AVSLD
|
|
AVSRD
|
|
AVSA
|
|
AVSRAB
|
|
AVSRAH
|
|
AVSRAW
|
|
AVSRAD
|
|
AVSOI
|
|
AVSLDOI
|
|
AVCLZ
|
|
AVCLZB
|
|
AVCLZH
|
|
AVCLZW
|
|
AVCLZD
|
|
AVPOPCNT
|
|
AVPOPCNTB
|
|
AVPOPCNTH
|
|
AVPOPCNTW
|
|
AVPOPCNTD
|
|
AVCMPEQ
|
|
AVCMPEQUB
|
|
AVCMPEQUBCC
|
|
AVCMPEQUH
|
|
AVCMPEQUHCC
|
|
AVCMPEQUW
|
|
AVCMPEQUWCC
|
|
AVCMPEQUD
|
|
AVCMPEQUDCC
|
|
AVCMPGT
|
|
AVCMPGTUB
|
|
AVCMPGTUBCC
|
|
AVCMPGTUH
|
|
AVCMPGTUHCC
|
|
AVCMPGTUW
|
|
AVCMPGTUWCC
|
|
AVCMPGTUD
|
|
AVCMPGTUDCC
|
|
AVCMPGTSB
|
|
AVCMPGTSBCC
|
|
AVCMPGTSH
|
|
AVCMPGTSHCC
|
|
AVCMPGTSW
|
|
AVCMPGTSWCC
|
|
AVCMPGTSD
|
|
AVCMPGTSDCC
|
|
AVCMPNEZB
|
|
AVCMPNEZBCC
|
|
AVCMPNEB
|
|
AVCMPNEBCC
|
|
AVCMPNEH
|
|
AVCMPNEHCC
|
|
AVCMPNEW
|
|
AVCMPNEWCC
|
|
AVPERM
|
|
AVPERMXOR
|
|
AVPERMR
|
|
AVBPERMQ
|
|
AVBPERMD
|
|
AVSEL
|
|
AVSPLT
|
|
AVSPLTB
|
|
AVSPLTH
|
|
AVSPLTW
|
|
AVSPLTI
|
|
AVSPLTISB
|
|
AVSPLTISH
|
|
AVSPLTISW
|
|
AVCIPH
|
|
AVCIPHER
|
|
AVCIPHERLAST
|
|
AVNCIPH
|
|
AVNCIPHER
|
|
AVNCIPHERLAST
|
|
AVSBOX
|
|
AVSHASIGMA
|
|
AVSHASIGMAW
|
|
AVSHASIGMAD
|
|
AVMRGEW
|
|
AVMRGOW
|
|
|
|
/* VSX */
|
|
ALXV
|
|
ALXVL
|
|
ALXVLL
|
|
ALXVD2X
|
|
ALXVW4X
|
|
ALXVH8X
|
|
ALXVB16X
|
|
ALXVX
|
|
ALXVDSX
|
|
ASTXV
|
|
ASTXVL
|
|
ASTXVLL
|
|
ASTXVD2X
|
|
ASTXVW4X
|
|
ASTXVH8X
|
|
ASTXVB16X
|
|
ASTXVX
|
|
ALXSDX
|
|
ASTXSDX
|
|
ALXSIWAX
|
|
ALXSIWZX
|
|
ASTXSIWX
|
|
AMFVSRD
|
|
AMFFPRD
|
|
AMFVRD
|
|
AMFVSRWZ
|
|
AMFVSRLD
|
|
AMTVSRD
|
|
AMTFPRD
|
|
AMTVRD
|
|
AMTVSRWA
|
|
AMTVSRWZ
|
|
AMTVSRDD
|
|
AMTVSRWS
|
|
AXXLAND
|
|
AXXLANDC
|
|
AXXLEQV
|
|
AXXLNAND
|
|
AXXLOR
|
|
AXXLORC
|
|
AXXLNOR
|
|
AXXLORQ
|
|
AXXLXOR
|
|
AXXSEL
|
|
AXXMRGHW
|
|
AXXMRGLW
|
|
AXXSPLT
|
|
AXXSPLTW
|
|
AXXSPLTIB
|
|
AXXPERM
|
|
AXXPERMDI
|
|
AXXSLDWI
|
|
AXXBRQ
|
|
AXXBRD
|
|
AXXBRW
|
|
AXXBRH
|
|
AXSCVDPSP
|
|
AXSCVSPDP
|
|
AXSCVDPSPN
|
|
AXSCVSPDPN
|
|
AXVCVDPSP
|
|
AXVCVSPDP
|
|
AXSCVDPSXDS
|
|
AXSCVDPSXWS
|
|
AXSCVDPUXDS
|
|
AXSCVDPUXWS
|
|
AXSCVSXDDP
|
|
AXSCVUXDDP
|
|
AXSCVSXDSP
|
|
AXSCVUXDSP
|
|
AXVCVDPSXDS
|
|
AXVCVDPSXWS
|
|
AXVCVDPUXDS
|
|
AXVCVDPUXWS
|
|
AXVCVSPSXDS
|
|
AXVCVSPSXWS
|
|
AXVCVSPUXDS
|
|
AXVCVSPUXWS
|
|
AXVCVSXDDP
|
|
AXVCVSXWDP
|
|
AXVCVUXDDP
|
|
AXVCVUXWDP
|
|
AXVCVSXDSP
|
|
AXVCVSXWSP
|
|
AXVCVUXDSP
|
|
AXVCVUXWSP
|
|
|
|
ALAST
|
|
|
|
// aliases
|
|
ABR = obj.AJMP
|
|
ABL = obj.ACALL
|
|
)
|