650 lines
11 KiB
Go
650 lines
11 KiB
Go
// Copyright 2014 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Package x86asm implements decoding of x86 machine code.
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package x86asm
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import (
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"bytes"
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"fmt"
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)
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// An Inst is a single instruction.
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type Inst struct {
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Prefix Prefixes // Prefixes applied to the instruction.
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Op Op // Opcode mnemonic
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Opcode uint32 // Encoded opcode bits, left aligned (first byte is Opcode>>24, etc)
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Args Args // Instruction arguments, in Intel order
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Mode int // processor mode in bits: 16, 32, or 64
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AddrSize int // address size in bits: 16, 32, or 64
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DataSize int // operand size in bits: 16, 32, or 64
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MemBytes int // size of memory argument in bytes: 1, 2, 4, 8, 16, and so on.
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Len int // length of encoded instruction in bytes
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PCRel int // length of PC-relative address in instruction encoding
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PCRelOff int // index of start of PC-relative address in instruction encoding
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}
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// Prefixes is an array of prefixes associated with a single instruction.
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// The prefixes are listed in the same order as found in the instruction:
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// each prefix byte corresponds to one slot in the array. The first zero
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// in the array marks the end of the prefixes.
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type Prefixes [14]Prefix
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// A Prefix represents an Intel instruction prefix.
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// The low 8 bits are the actual prefix byte encoding,
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// and the top 8 bits contain distinguishing bits and metadata.
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type Prefix uint16
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const (
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// Metadata about the role of a prefix in an instruction.
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PrefixImplicit Prefix = 0x8000 // prefix is implied by instruction text
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PrefixIgnored Prefix = 0x4000 // prefix is ignored: either irrelevant or overridden by a later prefix
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PrefixInvalid Prefix = 0x2000 // prefix makes entire instruction invalid (bad LOCK)
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// Memory segment overrides.
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PrefixES Prefix = 0x26 // ES segment override
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PrefixCS Prefix = 0x2E // CS segment override
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PrefixSS Prefix = 0x36 // SS segment override
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PrefixDS Prefix = 0x3E // DS segment override
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PrefixFS Prefix = 0x64 // FS segment override
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PrefixGS Prefix = 0x65 // GS segment override
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// Branch prediction.
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PrefixPN Prefix = 0x12E // predict not taken (conditional branch only)
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PrefixPT Prefix = 0x13E // predict taken (conditional branch only)
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// Size attributes.
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PrefixDataSize Prefix = 0x66 // operand size override
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PrefixData16 Prefix = 0x166
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PrefixData32 Prefix = 0x266
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PrefixAddrSize Prefix = 0x67 // address size override
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PrefixAddr16 Prefix = 0x167
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PrefixAddr32 Prefix = 0x267
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// One of a kind.
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PrefixLOCK Prefix = 0xF0 // lock
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PrefixREPN Prefix = 0xF2 // repeat not zero
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PrefixXACQUIRE Prefix = 0x1F2
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PrefixBND Prefix = 0x2F2
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PrefixREP Prefix = 0xF3 // repeat
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PrefixXRELEASE Prefix = 0x1F3
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// The REX prefixes must be in the range [PrefixREX, PrefixREX+0x10).
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// the other bits are set or not according to the intended use.
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PrefixREX Prefix = 0x40 // REX 64-bit extension prefix
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PrefixREXW Prefix = 0x08 // extension bit W (64-bit instruction width)
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PrefixREXR Prefix = 0x04 // extension bit R (r field in modrm)
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PrefixREXX Prefix = 0x02 // extension bit X (index field in sib)
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PrefixREXB Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib)
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PrefixVEX2Bytes Prefix = 0xC5 // Short form of vex prefix
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PrefixVEX3Bytes Prefix = 0xC4 // Long form of vex prefix
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)
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// IsREX reports whether p is a REX prefix byte.
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func (p Prefix) IsREX() bool {
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return p&0xF0 == PrefixREX
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}
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func (p Prefix) IsVEX() bool {
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return p&0xFF == PrefixVEX2Bytes || p&0xFF == PrefixVEX3Bytes
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}
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func (p Prefix) String() string {
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p &^= PrefixImplicit | PrefixIgnored | PrefixInvalid
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if s := prefixNames[p]; s != "" {
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return s
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}
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if p.IsREX() {
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s := "REX."
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if p&PrefixREXW != 0 {
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s += "W"
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}
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if p&PrefixREXR != 0 {
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s += "R"
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}
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if p&PrefixREXX != 0 {
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s += "X"
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}
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if p&PrefixREXB != 0 {
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s += "B"
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}
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return s
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}
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return fmt.Sprintf("Prefix(%#x)", int(p))
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}
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// An Op is an x86 opcode.
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type Op uint32
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func (op Op) String() string {
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i := int(op)
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if i < 0 || i >= len(opNames) || opNames[i] == "" {
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return fmt.Sprintf("Op(%d)", i)
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}
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return opNames[i]
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}
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// An Args holds the instruction arguments.
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// If an instruction has fewer than 4 arguments,
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// the final elements in the array are nil.
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type Args [4]Arg
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// An Arg is a single instruction argument,
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// one of these types: Reg, Mem, Imm, Rel.
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type Arg interface {
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String() string
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isArg()
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}
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// Note that the implements of Arg that follow are all sized
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// so that on a 64-bit machine the data can be inlined in
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// the interface value instead of requiring an allocation.
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// A Reg is a single register.
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// The zero Reg value has no name but indicates ``no register.''
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type Reg uint8
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const (
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_ Reg = iota
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// 8-bit
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AL
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CL
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DL
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BL
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AH
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CH
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DH
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BH
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SPB
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BPB
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SIB
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DIB
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R8B
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R9B
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R10B
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R11B
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R12B
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R13B
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R14B
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R15B
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// 16-bit
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AX
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CX
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DX
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BX
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SP
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BP
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SI
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DI
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R8W
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R9W
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R10W
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R11W
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R12W
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R13W
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R14W
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R15W
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// 32-bit
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EAX
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ECX
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EDX
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EBX
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ESP
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EBP
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ESI
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EDI
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R8L
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R9L
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R10L
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R11L
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R12L
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R13L
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R14L
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R15L
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// 64-bit
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RAX
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RCX
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RDX
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RBX
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RSP
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RBP
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RSI
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RDI
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R8
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R9
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R10
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R11
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R12
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R13
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R14
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R15
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// Instruction pointer.
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IP // 16-bit
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EIP // 32-bit
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RIP // 64-bit
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// 387 floating point registers.
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F0
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F1
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F2
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F3
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F4
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F5
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F6
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F7
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// MMX registers.
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M0
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M1
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M2
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M3
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M4
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M5
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M6
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M7
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// XMM registers.
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X0
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X1
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X2
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X3
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X4
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X5
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X6
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X7
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X8
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X9
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X10
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X11
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X12
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X13
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X14
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X15
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// Segment registers.
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ES
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CS
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SS
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DS
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FS
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GS
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// System registers.
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GDTR
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IDTR
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LDTR
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MSW
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TASK
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// Control registers.
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CR0
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CR1
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CR2
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CR3
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CR4
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CR5
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CR6
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CR7
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CR8
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CR9
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CR10
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CR11
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CR12
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CR13
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CR14
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CR15
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// Debug registers.
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DR0
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DR1
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DR2
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DR3
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DR4
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DR5
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DR6
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DR7
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DR8
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DR9
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DR10
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DR11
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DR12
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DR13
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DR14
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DR15
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// Task registers.
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TR0
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TR1
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TR2
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TR3
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TR4
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TR5
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TR6
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TR7
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)
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const regMax = TR7
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func (Reg) isArg() {}
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func (r Reg) String() string {
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i := int(r)
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if i < 0 || i >= len(regNames) || regNames[i] == "" {
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return fmt.Sprintf("Reg(%d)", i)
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}
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return regNames[i]
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}
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// A Mem is a memory reference.
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// The general form is Segment:[Base+Scale*Index+Disp].
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type Mem struct {
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Segment Reg
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Base Reg
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Scale uint8
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Index Reg
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Disp int64
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}
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func (Mem) isArg() {}
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func (m Mem) String() string {
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var base, plus, scale, index, disp string
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if m.Base != 0 {
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base = m.Base.String()
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}
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if m.Scale != 0 {
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if m.Base != 0 {
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plus = "+"
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}
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if m.Scale > 1 {
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scale = fmt.Sprintf("%d*", m.Scale)
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}
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index = m.Index.String()
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}
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if m.Disp != 0 || m.Base == 0 && m.Scale == 0 {
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disp = fmt.Sprintf("%+#x", m.Disp)
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}
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return "[" + base + plus + scale + index + disp + "]"
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}
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// A Rel is an offset relative to the current instruction pointer.
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type Rel int32
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func (Rel) isArg() {}
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func (r Rel) String() string {
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return fmt.Sprintf(".%+d", r)
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}
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// An Imm is an integer constant.
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type Imm int64
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func (Imm) isArg() {}
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func (i Imm) String() string {
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return fmt.Sprintf("%#x", int64(i))
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}
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func (i Inst) String() string {
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var buf bytes.Buffer
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for _, p := range i.Prefix {
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if p == 0 {
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break
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}
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if p&PrefixImplicit != 0 {
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continue
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}
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fmt.Fprintf(&buf, "%v ", p)
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}
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fmt.Fprintf(&buf, "%v", i.Op)
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sep := " "
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for _, v := range i.Args {
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if v == nil {
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break
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}
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fmt.Fprintf(&buf, "%s%v", sep, v)
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sep = ", "
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}
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return buf.String()
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}
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func isReg(a Arg) bool {
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_, ok := a.(Reg)
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return ok
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}
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func isSegReg(a Arg) bool {
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r, ok := a.(Reg)
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return ok && ES <= r && r <= GS
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}
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func isMem(a Arg) bool {
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_, ok := a.(Mem)
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return ok
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}
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func isImm(a Arg) bool {
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_, ok := a.(Imm)
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return ok
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}
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func regBytes(a Arg) int {
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r, ok := a.(Reg)
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if !ok {
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return 0
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}
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if AL <= r && r <= R15B {
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return 1
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}
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if AX <= r && r <= R15W {
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return 2
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}
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if EAX <= r && r <= R15L {
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return 4
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}
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if RAX <= r && r <= R15 {
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return 8
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}
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return 0
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}
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func isSegment(p Prefix) bool {
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switch p {
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case PrefixCS, PrefixDS, PrefixES, PrefixFS, PrefixGS, PrefixSS:
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return true
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}
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return false
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}
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// The Op definitions and string list are in tables.go.
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var prefixNames = map[Prefix]string{
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PrefixCS: "CS",
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PrefixDS: "DS",
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PrefixES: "ES",
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PrefixFS: "FS",
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PrefixGS: "GS",
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PrefixSS: "SS",
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PrefixLOCK: "LOCK",
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PrefixREP: "REP",
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PrefixREPN: "REPN",
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PrefixAddrSize: "ADDRSIZE",
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PrefixDataSize: "DATASIZE",
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PrefixAddr16: "ADDR16",
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PrefixData16: "DATA16",
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PrefixAddr32: "ADDR32",
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PrefixData32: "DATA32",
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PrefixBND: "BND",
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PrefixXACQUIRE: "XACQUIRE",
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PrefixXRELEASE: "XRELEASE",
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PrefixREX: "REX",
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PrefixPT: "PT",
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PrefixPN: "PN",
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}
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var regNames = [...]string{
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AL: "AL",
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CL: "CL",
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BL: "BL",
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DL: "DL",
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AH: "AH",
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CH: "CH",
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BH: "BH",
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DH: "DH",
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SPB: "SPB",
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BPB: "BPB",
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SIB: "SIB",
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DIB: "DIB",
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R8B: "R8B",
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R9B: "R9B",
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R10B: "R10B",
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R11B: "R11B",
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R12B: "R12B",
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R13B: "R13B",
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R14B: "R14B",
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R15B: "R15B",
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AX: "AX",
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CX: "CX",
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BX: "BX",
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DX: "DX",
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SP: "SP",
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BP: "BP",
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SI: "SI",
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DI: "DI",
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R8W: "R8W",
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R9W: "R9W",
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R10W: "R10W",
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R11W: "R11W",
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R12W: "R12W",
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R13W: "R13W",
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R14W: "R14W",
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R15W: "R15W",
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EAX: "EAX",
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ECX: "ECX",
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EDX: "EDX",
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EBX: "EBX",
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ESP: "ESP",
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EBP: "EBP",
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ESI: "ESI",
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EDI: "EDI",
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R8L: "R8L",
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R9L: "R9L",
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R10L: "R10L",
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R11L: "R11L",
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R12L: "R12L",
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R13L: "R13L",
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R14L: "R14L",
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R15L: "R15L",
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RAX: "RAX",
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RCX: "RCX",
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RDX: "RDX",
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RBX: "RBX",
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RSP: "RSP",
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RBP: "RBP",
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RSI: "RSI",
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RDI: "RDI",
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R8: "R8",
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R9: "R9",
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R10: "R10",
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R11: "R11",
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R12: "R12",
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R13: "R13",
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R14: "R14",
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R15: "R15",
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IP: "IP",
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EIP: "EIP",
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RIP: "RIP",
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F0: "F0",
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F1: "F1",
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F2: "F2",
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F3: "F3",
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F4: "F4",
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F5: "F5",
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F6: "F6",
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F7: "F7",
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M0: "M0",
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M1: "M1",
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M2: "M2",
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M3: "M3",
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M4: "M4",
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M5: "M5",
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M6: "M6",
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M7: "M7",
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X0: "X0",
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X1: "X1",
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X2: "X2",
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X3: "X3",
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X4: "X4",
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X5: "X5",
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X6: "X6",
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X7: "X7",
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X8: "X8",
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X9: "X9",
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X10: "X10",
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X11: "X11",
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X12: "X12",
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X13: "X13",
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X14: "X14",
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X15: "X15",
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CS: "CS",
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SS: "SS",
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DS: "DS",
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ES: "ES",
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FS: "FS",
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GS: "GS",
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GDTR: "GDTR",
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IDTR: "IDTR",
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LDTR: "LDTR",
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MSW: "MSW",
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TASK: "TASK",
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CR0: "CR0",
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CR1: "CR1",
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CR2: "CR2",
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CR3: "CR3",
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CR4: "CR4",
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CR5: "CR5",
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CR6: "CR6",
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CR7: "CR7",
|
|
CR8: "CR8",
|
|
CR9: "CR9",
|
|
CR10: "CR10",
|
|
CR11: "CR11",
|
|
CR12: "CR12",
|
|
CR13: "CR13",
|
|
CR14: "CR14",
|
|
CR15: "CR15",
|
|
DR0: "DR0",
|
|
DR1: "DR1",
|
|
DR2: "DR2",
|
|
DR3: "DR3",
|
|
DR4: "DR4",
|
|
DR5: "DR5",
|
|
DR6: "DR6",
|
|
DR7: "DR7",
|
|
DR8: "DR8",
|
|
DR9: "DR9",
|
|
DR10: "DR10",
|
|
DR11: "DR11",
|
|
DR12: "DR12",
|
|
DR13: "DR13",
|
|
DR14: "DR14",
|
|
DR15: "DR15",
|
|
TR0: "TR0",
|
|
TR1: "TR1",
|
|
TR2: "TR2",
|
|
TR3: "TR3",
|
|
TR4: "TR4",
|
|
TR5: "TR5",
|
|
TR6: "TR6",
|
|
TR7: "TR7",
|
|
}
|